MityDSP-L138 Carrier Board Design Guide
March 5, 2014
Page 2 of 17
Document Revision: 1.7
– MityDSP-L138 Revision 4A
Critical Link reserves the right to make corrections, modifications, enhancements, and other changes to this document at any time and without notice.
Each module includes power management, DDR2 SDRAM, NAND and NOR Flash memories, and is interfaced by a
200-pin low-profile SO-DIMM card-edge connector. Carrier board design for these types of MityDSP is the main
focus of this document.
The 2
nd
generation module, the MityDSP-Pro (MityDSP-6455), is based on a Texas Instruments TMS320C645x
DSP, includes DDR2 SDRAM and Flash memories, and is interfaced by the same 200-pin SO-DIMM card-edge
connector and a 100-pin high-density, low-profile Hirose connector. The module integrates a large Xilinx
Spartan3 FPGA for implementing required on-board logic and I/O interfaces, but primarily for end-user
customizable logic and I/O interfaces. The module also incorporates a number of high bandwidth I/O interfaces
including: PCI/HPI, Serial RapidIO, and Gigabit Ethernet interfaces provided by the DSP; and DDR SDRAM
dedicated to the FPGA.
The 1
st
generation family of modules, the MityDSP and MityDSP-XM (MityDSP-6711 and MityDSP-6711XM), are
based on a Texas Instruments TMS3206711 DSP, include SDRAM and Flash memories, and are interfaced using a
144-pin SO-DIMM card edge connector. The module integrates a Xilinx Spartan 3 FPGA for implementing
required on-board logic and I/O interfaces.
All types of MityDSP are available with options for speed grade, memory size, FPGA size (or complete removal),
operating temperature ranges, and RoHS / non-RoHS compliance. Please contact Critical Link for the current list
of MityDSP and MitySOM variants.
1.4
MityDSP-L138F Family Modules (With FPGA)
An available option to the MityDSP-L138 family of modules is a module that includes a Spartan6 FPGA. This unit
is slightly larger than the non-FPGA module, and it requires slightly more power to run. Many of the IO pins
previously reserved for SoC functions have been instead routed to FPGA pins, but those functions are still
available by passing them through the FPGA. The difference in the part name is the addition of the “F” at the
end. See the datasheets and design guide for these parts for pin-out information.
