MityDSP-L138 Carrier Board Design Guide
March 5, 2014
Page 12 of 17
Document Revision: 1.7
– MityDSP-L138 Revision 4A
Critical Link reserves the right to make corrections, modifications, enhancements, and other changes to this document at any time and without notice.
reserved in order to support booting from the on-board NOR flash. After bootloading, access to the NOR flash is
typically not required, and the SPI port may be used with other chip selects if required. The SPI ports share pins
with other peripherals on the SOC processor. Refer to the SOC datasheet for more details.
3.3.8
I2C Ports
All modules include support for up to 2 Inter-Integrated Circuit (I2C) ports. I2C0 is connected to an on-board
prom (address 1010XXXb) that is used to hold factory configuration data (serial number, MAC address, etc.) and
is therefore dedicated to this function. I2C0 is also connected to an on-board Power Management Integrated
Circuit (PMIC), the TPS65023 (address 1001000b). Users may use the I2C0 port however, to interface to other
devices having different addresses than those mentioned on this bus. The I2C ports share pins with other
peripherals on the SOC processor. Refer to the SOC datasheet for more details.
3.3.9
10/100 Ethernet
Ethernet on the MityDSP-L138, MitySOM-1808, MitySOM-1810, or MityDSP-6748 is available as a MAC core in
the CPU SOC. This Ethernet MAC is capable of full and half duplex 10/100 Mbit operation. To complete the
interface, the MAC core requires a physical-layer device (PHY), an Ethernet isolation transformer (H1102 or
equivalent), and an RJ-45 style connector (RJHSE-5381 or equivalent) on the carrier board. A connector with
integrated magnetics and passives may also be used in place of discrete components.
All of the SOCs in this family of MityDSP (OMAP-L138, Sitara-1808, Sitara-1810, and DSP6748) provide support
for both standard Media Independent Interface (MII) and Reduced Media Independent Interface (RMII) formats.
The MityDSP-L138 family of SOMs expose the RMII SOC interface directly to the edge connector. In general,
designs requiring Ethernet should use the MII interface with MityDSP-L138 family SOMS. However, the RMII
interface may still be used if the UPP and Video-Port-In functions are not needed.
The PHY IC’s commonly used by Critical Link are the TI TLK100, and SMSC LAN87x0 family. It is also possible to
connect the MAC core directly to an Ethernet Switch IC, such as the Micrel KS8995, via its standard Ethernet MII
port. This option gives the carrier board the flexibility of easily making connections with several other Ethernet
devices, without the need for additional networking equipment.
3.3.10
USB
The SOC provides two Universal Serial Bus (USB) interfaces that are mapped directly to the edge connector of
the module. One port is capable of running as a host controller using USB 1.1 compliant protocols. The second
port is capable of operating using the On-The-Go (OTG) protocol and is USB 2.0 compliant. OTG protocols
support dynamic switching from host mode (e.g., for controlling USB mass storage devices such as thumb drives)
to client mode (e.g., for interfacing to a PC) based on application software. For details in implementing the USB
physical interface, refer to the TI SOC datasheets. The USB functions are not multiplexed with any other
interfaces on the module.
