
3-10 BIOS Setup
PCI Peer
Concurrency
When enabled, more than one device on the PCI bus can be active
at the same time.
PCI Delay
Transaction
Can be enabled if the computer has an embedded 32-bit write buffer
to support delay transaction cycles. Recommended: Leave this item
at the default value.
XXX Driving Rate
Controls system timing. Recommended: Leave this item at the
default value.
SDRCLK
SDWCLK
Controls system timing. Recommended: Leave this item at the
default value.
Refresh Queue
Depth
Controls system timing. Recommended: Leave this item at the
default value.
Host2PCI/
Host2Mem Cycle
Time
Controls system timing. Recommended: Leave this item at the
default value.
M009-3.fm Page 10 Wednesday, May 19, 1999 1:33 PM