6. About Hardware
88
AD12-16(PCI)E, AD12-16U(PCI)E, AD16-16(PCI)E
Timing of Sampling Control Signals
There are timing chart diagrams and a table about sampling control signals as shown Fig.6.2, 6.3, 6.4
and Table 6.5.
t
DEC
External Smapling Clock Input
t
DEH
Conversion start
Sample / Hold
Figure 6.2. Timing Chart of External Sampling Clock
External Smapling Start Trigger Input
t
HRS
t
SRS
t
HFS
t
SFS
Figure 6.3. Timing Chart of External Sampling Start Control Signal
External Smapling Stop Trigger Input
t
HRP
t
SRP
t
HFP
t
SFP
Figure 6.4. Timing Chart of External Sampling Stop Control Signal
Table 6.5. Timing Table of Operation Control Signals
Parameter
Symbol
Time
Unit
Delay time from external sampling clock to first hold action
tDEH
100
nsec
Delay time from external sampling clock to first A/D start pulse
tDEC
100
nsec
Set up time of sampling start (Rising edge)
tSRS
100
nsec
Hold time of sampling start (Rising edge)
tHRS
100
nsec
Set up time of sampling start (Rising edge)
tSFS
100
nsec
Hold time of sampling start (Rising edge)
tHFS
100
nsec
Set up time of sampling stop (Rising edge)
tSRP
100
nsec
Hold time of sampling stop (Rising edge)
tHRP
100
nsec
Set up time of sampling stop (Rising edge)
tSFP
100
nsec
Hold time of sampling stop (Rising edge)
tHFP
100
nsec
CAUTION
All of the times in Table 6.5 are typical values.
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