Contec PC-686CPCI-LV, Руководство пользователя

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CHAPTER 4 – CPU Board Resources
PC-686 (CPCI)-LV User’s Manual 47
4.6. PCI Interrupters Routing Map
This section describes interrupt sharing and how the interrupt signals are
connected between the PCI expansion slots and onboard PCI devices. The PCI
specification specifies how interrupts can be shared between devices attached to the
PCI bus. In most cases, the small amount of latency added by interrupt sharing
does not affect the operation or throughput of the devices. In some special cases
where maximum performance is needed from a device, a PCI device should not
share an interrupt with other PCI devices. Use the following information to avoid
sharing an interrupt with a PCI add-in board.
PCI devices are categorized as follows to specify their interrupt grouping:
- INTA: By default, all add-in board that require only one interrupt are in this
category. For almost all board that require more than one interrupt, the first
interrupt on the board is also classified as INTA.
- INTB: Generally, the second interrupt on add-in
board
that require two or more
interrupts is classified as INTB. (This is not an absolute requirement.)
- INTC and INTD: Generally, a third interrupt on add-in board is classified as
INTC and a fourth interrupt is classified as INTD.
The PIIX4E PCI-to-ISA bridge has four programmable interrupt request
(PIRQ) input signals. Any PCI interrupt source (either onboard or from a PCI add-
in board) connects to one of these PIRQ signals. Because there are only four
signals, some PCI interrupt sources are mechanically tied together on the CPU
board and therefore share the same interrupt. The table below lists the PIRQ
signals and shows how the signals are connected to the onboard PCI interrupt
sources.