Contec PC-686BX(NLX)-LV, Руководство пользователя

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7. BIOS Setup
PC-686BX(NLX)-LV, PC-686BX(NLX)-LVV
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Chipset Features Setup
Power-Supply Type : At
Auto Detect DIMM/PCI Clk : Enabled
Spread Spectrum : Disabled
CPU Host Clock (CPU/PCI) : Default
CPU Warning Temperature : Disabled
Current System Temp. :
Current CPU1 Temperature :
Current CPUFAN1 Speed :
Current CPUFAN2 Speed :
Current CPUFAN3 Speed :
Vcore : VTT :
+3.3 V : + 5 V :
+12 V : -12 V :-
- 5 V :
Auto Configuration : Disabled
EDO DRAM Speed Selection : 60ns
EDO CASx# MA Wait State : 1
EDO RASx# Wait State : 1
SDRAM RAS-to-CAS Delay : 3
SDRAM RAS Precharge Time : 3
SDRAM CAS latency Time : 2
SDRAM Precharge Control : Disabled
DRAM Data Integrity Mode : Non-ECC
System BIOS Cacheable : Disabled
Video BIOS Cacheable : Disabled
Video RAM Cacheable : Disabled
8 Bit I/O Recovery Time : NA
16 Bit I/O Recovery Time : NA
Memory Hole At 15M-16M : Disabled
Passive Release : Disabled
Delayed Transaction : Disabled
AGP Aperture Size (MB) : 4
ESC : Quit : Select Item
F1 : Help PU/PD/+/- : Modify
F5 : Old Values (Shift)F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
The chipset features setup menu is used to configure the system for the functions
specific to the installed chipset. The chipset manages the bus speed and access to
system memory resources such as the DRAM and external cache. The chipset also
handles communication between the PCI bus and old-style ISA bus. It is important to
make clear that the settings described in this section must not be modified. The
default settings are selected because these achieve optimum system performance.
The only situation in which these settings may need to be modified is if data is erased
during system operation.
DRAM Settings
The above chipset settings apply to CPU access to the dynamic random access
memory (DRAM). The default timings are carefully chosen and therefore should
only be modified if data has been erased. This scenario may occur if DRAM chips
with different speeds are installed on the system and a longer delay needs to be used to
ensure the reliability of data stored on the low speed memory chips.