Copyright © 2006 congatec AG
C800m10
2/65
Signal
Description
I/O
PU/PD
Comment
USB_2_3_OC# USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be present
on the module. An open drain driver from a USB current monitor on the Carrier Board
may drive this line low. Do not pull this line high on the Carrier Board.
I 3.3V PU 10k 3.3V
Both over current pins USB_0_1_OC# and
USB_2_3_OC# are connected together
USB_4_5_OC# USB over-current sense, USB ports 4 and 5. A pull-up for this line shall be present
on the module. An open drain driver from a USB current monitor on the Carrier Board
may drive this line low. Do not pull this line high on the Carrier Board.
I
Not supported
USB_6_7_OC# USB over-current sense, USB ports 6 and 7. A pull-up for this line shall be present
on the module. An open drain driver from a USB current monitor on the Carrier Board
may drive this line low. Do not pull this line high on the Carrier Board.
I
Not supported
Table 10 CRT Signal Descriptions
Signal
Description
I/O
PU/PD
Comment
VGA_RED
Red for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.
O Analog
PD 150R
Analog output
VGA_GRN
Green for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.
O Analog
PD 150R
Analog output
VGA_BLU
Blue for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.
O Analog
PD 150R
Analog output
VGA_HSYNC
Horizontal sync output to VGA monitor
O 3.3V
5V tolerant
VGA_VSYNC
Vertical sync output to VGA monitor
O 3.3V
5V tolerant
VGA_I2C_CK
DDC clock line (I²C port dedicated to identify VGA monitor capabilities)
I/O
PU 2k2 3.3V
VGA_I2C_DAT DDC data line.
I/O
PU 2k2 3.3V
Table 11 LVDS Signal Descriptions
Signal
Description
I/O
PU/PD
Comment
LVDS_A[0:2]+
LVDS_A[0:2]-
LVDS Channel A differential pairs
O LVDS
LVDS 1 channel 18bit
LVDS_A3-
LVDS Channel A differential pairs
O LVDS
Not supported
LV
LVDS_A_CK-
LVDS Channel A differential clock
O LVDS
LVDS_B[0:3]+
LVDS_B[0:3]-
LVDS Channel B differential pairs
O LVDS
Not supported
LV
LVDS_B_CK-
LVDS Channel B differential clock
O LVDS
Not supported
LVDS_VDD_EN
LVDS panel power enable
O 3.3V
PU 10k 3.3V
LVDS_BKLT_EN
LVDS panel backlight enable
O 3.3V
LVDS_BKLT_CTRL LVDS panel backlight brightness control
O
Not supported
LVDS_I2C_CK
DDC lines used for flat panel detection and control.
O 3.3V
PU 10k 3.3V
LVDS_I2C_DAT
DDC lines used for flat panel detection and control.
I/O 3.3V
PU 10k 3.3V
