Conexant Fusion 878A, Руководство пользователя

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Fusion 878A
2.0 Functional Description
PCI Video Decoder 2.12 DMA Controller
100600B
Conexant
2-37
2.12.1 Target Memory
The Fusion 878A’s FIFO DWORDs are perfectly aligned to the PCI bus: i.e., bit 0
of the FIFO DWORDs lines up with bit AD[0] on the PCI bus. Thus, video scan
line data is aligned to target memory locations, and data path combinational logic
between the FIFO and the PCI bus is not required.
The target memory for a given scan line of data is assumed to be linear,
incrementing, and contiguous. For a 1024-pixel scan line, a maximum of 4 kB of
contiguous physical memory is required. Each scan line can be stored anywhere
in the 32-bit address space. A scan line can be broken into segments with each
segment sent to a different target area. An image buffer can be allocated to line
fragments anywhere in the physical memory, because the line sequence is
arbitrary.
2.12.2 RISC Program Setup and Synchronization
There are two independent sets of RISC instructions in the host memory: one for
the odd field and the other for the even field. The first field begins with a
synchronization instruction (See SYNC in
Table 2-10 ) indicating packed or
planar data from the FIFO (STATUS[3:0] = FM1 or FM3). The first field ends
with a SYNC instruction indicating an even or an odd field to follow
(STATUS[3:0] = VRE or VRO). The second field begins with a SYNC
instruction and ends with a SYNC instruction followed by a JUMP instruction
back to the first field. The SYNC instructions allow the synchronization of the
FIFO output and the RISC program start/end points.
Figure 2-21. Audio/Video RISC Block Diagram
From
FIFO
RISC
Instruction
Buffer
DMA
Address
and
Byte Counter
FIFO Data
Buffer
RISC
Program
Counter
Address/Data
Decoder
RISC
Decoder
PCI
Initiator
Control Signals
Op
Code
To PCI Bus
Interface
Pixel Data [31:0]
RISC
Instructions
FIFO Read
Signals
FIFO Status
Bits
Number of
bytes
available
in FIFO
FIFO
Output [31:0]
DMA Controller
Address
RISC Program
Start Address
879A_026