Conexant Fusion 878A, Руководство пользователя

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1.0 Product Overview
Fusion 878A
1.3 Pin Descriptions PCI Video Decoder
1-10
Conexant
100600B
25 FRAME I/O Cycle Frame This sustained, three-state signal is driven by the current master
to indicate the beginning and duration of an access. FRAME is
asserted to signal the beginning of a bus transaction. Data
transfer continues throughout assertion. At de-assertion, the
transaction is in the final data phase.
26 IRDY I/O Initiator Ready This sustained, three-state signal indicates the bus master’s
readiness to complete the current data phase.
IRDY is used in conjunction with TRDY. When both IRDY and
TRDY are asserted, a data phase is completed on that clock.
During a read, IRDY indicates when the initiator is ready to
accept data. During a write, IRDY indicates when the initiator
has placed valid data on AD[31:0]. Wait cycles are inserted until
both IRDY and TRDY are asserted together.
28 DEVSEL I/O Device Select This sustained, three-state signal indicates device selection.
When actively driven, DEVSEL indicates the driving device has
decoded its address as the target of the current access.
27 TRDY I/O Target Ready This sustained, three-state signal indicates the target’s
readiness to complete the current data phase.
IRDY is used in conjunction with TRDY. When both IRDY and
TRDY are asserted, a data phase is completed on that clock.
During a read, TRDY indicates when the target is presenting
data. During a write, TRDY indicates when the target is ready to
accept the data. Wait cycles are inserted until both IRDY and
TRDY are asserted together.
29 STOP I/O Stop This sustained, three-state signal indicates the target is
requesting the master to stop the current transaction.
30 PERR I/O Parity Error Report data parity error.
31 SERR O System Error Report address parity error. Open drain.
126 INTA O Interrupt A This signal is an open drain interrupt output.
JTAG (5 Pins)
122 TCK I Test Clock Used to synchronize all JTAG test structures. When JTAG
operations are not being performed, this pin must be driven to a
logical low.
123 TMS I Test Mode Select JTAG input pin whose transitions drive the JTAG state machine
through its sequences. When JTAG operations are not being
performed, this pin must be left floating or tied high.
125 TDI I Test Data Input JTAG pin used for loading instructions to the TAP controller or
for loading test vector data for boundary-scan operation. When
JTAG operations are not being performed, this pin must be left
floating or tied high.
124 TDO O Test Data Output JTAG pin used for verifying test results of all JTAG sampling
operations. This output pin is active for certain JTAG operations
and will be three-stated at all other times.
121 TRST I Test Reset JTAG pin used to initialize the JTAG controller. When JTAG
operations are not being performed, this pin must be driven to a
logical low.
Table 1-2. Pin Descriptions Grouped by Pin Function (2 of 4)
Pin # Pin Name I/O Signal Description