Compaq iPAQ 1.0, Техническое справочное руководство

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Technical Reference Guide
Compaq iPAQ Series of Desktop Personal Computers
Second Edition - February 2001
4-5
Not required
The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration space
of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration data
(Figure 4-3), of which the first 64 bytes comprise the configuration space header.
Figure 4-3. PCI Configuration Space Mapping
Each PCI device is identified with a vendor ID (assigned to the vendor by the PCI Special Interest
Group) and a device ID (assigned by the vendor). The device and vendor IDs for the devices on
the system board are listed (previously) in Table 4-1.
4.2.2 PCI SUB-BUSSES
The chipset implements two data busses that are supplementary in operation to the PCI bus:
The chipset implements a Hub Link bus between the GMCH and the ICH. This bus is transparent
to software and not accessible for expansion purposes.
The 82801 ICH implements a Low Pin Count (LPC) bus for handling transactions to and from the
47B357 Super I/O Controller as well as the 82802 FWH. The LPC bus transfers data a nibble (4
bits) at a time at a 33-MHz rate. Generally transparent in operation, the LPC bus becomes a factor
primarily during the configuration of DMA channel modes (see section 4.4.3 “DMA”).
Data required by PCI protocol
Configuration
Space
Header
PCI Configuration Space Type 1
Class Code
Command
31 24 23 16 15 8 7 0
Revision ID
Vendor ID
Status
Device ID
Expansion ROM Base Address
Reserved
Prefetchable Limit Upper 32 Bits
Prefetch. Mem. Limit Prefetch. Mem. Base
Prefetchable Base Upper 32 Bits
Device-Specific Area
Line Size Lat. Timer
Int. Line Int. Pin
BIST Hdr. Type
Pri. Bus # Sec. Bus # Sub. Bus # 2
nd
00h
Register
Index
04h
08h
0Ch
2Ch
30h
FCh
18h
28h
3Ch
38h
34h
40h
Bridge Control
I/O Base Upper 16 Bits I/O Limit Upper 16 Bits
24h
20h
Memory Base Memory Limit
I/O Base I/O Limit Secondary Status
1Ch
10h
Base Address Registers
00h
Register
Index
04h
08h
0Ch
2Ch
30h
FCh
10h
28h
3Ch
38h
34h
40h
Command
31 24 23 16 15 8 7 0
Revision ID
Vendor ID
Status
Device ID
Reserved
Reserved
Expansion ROM Base Address
Subsystem Vendor ID Subsystem ID
Card Bus CIS Pointer
Device-Specific Area
Line Size Lat. Timer
Int. Line Int. Pin Min. GNT Min. Lat.
BIST Hdr. Type
Class Code
Base Address Registers
PCI Configuration Space Type 0