Compaq AlphaServer ES40, Руководство по обслуживанию

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Registers D-25
Table D–9 PCTX Register Fields
Name Extent Type Description
Reserved [63:47]
ASN[7:0] [46:39] RW Address space number.
Reserved [38:13]
ASTRR[3:0] [12:9] RW AST request register—used to request AST
interrupts in each of the four processor
modes.
To generate a particular AST interrupt, its
corresponding bits in ASTRR and ASTER
must be set, along with the ASTE bit in IER.
Further, the value of the current mode bits in
the PS register must be equal to or higher
than the value of the mode associated with
the AST request.
The bit order with this field is:
User Mode
Supervior Mode
Executive Mode
Kernel Mode
ASTER[3:0] [8:5] RW AST enable register—used to individually
enable each of the four AST interrupt
requests.
The bit order with this field is:
User Mode
Supervisor Mode
Executive Mode
Kernel Mode
Reserved [4:3]
FPE [2] RW,1 Floating-point enable—if clear, floating-
point instructions generate FEN exceptions.
This bit is set by hardware on reset.
PPCE [1] RW Process performance counting enable.
Enables performance counting for an
individual process with counters PCTR0 or
PCTR1, which are enabled by setting
PCT0_EN or PCT1_EN, respectively.
Performance counting for the entire system
can be enabled by setting I_CTL[SPCE].