CogniMem CM1K, Руководство пользователя

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CM1K Hardware User’s Manual
51
9 Physical specifications
9.1 Pinout
Bidir = Didirectional line, with open collector
PU= pull up
PD= pull down
Pin # Symbol Type Pull Description
1 RSVD Reserved
2 VCCIO IO power supply line (3.3 v)
3 G_Reset_ Global reset_low line
4 VCC Core power supply (1.2v)
5 I2C_EN Input PU I2C enable
6 CS_ Input PD Standby mode (interrupt chip activity)
7 VCCIO IO power supply line (3.3 v)
8 G_CLK Input
Master clock. Up to 27 Mhz for a single chip. Up to 13.5 Mhz for
a multiple-chip configuration.
9 VCCIO IO power supply line (3.3 v)
10 I2C_SDK Input I2C clock
11 VCC Core power supply (1.2v)
12 VCCIO IO power supply line (3.3 v)
13 DCI Input PU Daisy Chain In
14 VCC Core power supply (1.2v)
15 I2C_SDA IO PU I2C serial data line
16 V_EN Input PU Video enable
17 VCC Core power supply (1.2v)
18 V_DATA[0] Input Video data line 0
19 V_DATA[1] Input Video data line 1
20 VCC Core power supply (1.2v)
21 V_DATA[2] Input Video data line 2
22 VCC Core power supply (1.2v)
23 V_DATA[3] Input Video data line 3
24 V_DATA[4] Input Video data line 4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
100
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
DATA[5]
VCCIO
DATA[4]
VCC
VCCIO
VCC
DATA[3]
VCCIO
DATA[2]
VCC
DATA[1]
VCCIO
DATA[0]
DCO
VCC
VCC
VCCIO
DIST_VAL
GND
VCC
VCC
VCCIO
DS
RDY
VCCIO
RSVD
VCCIO
G_RESET
VCC
I2C_EN
STANDBY
VCCIO
G_CLK
VCCIO
I2C_SCK
VCC
VCCIO
DCI
VCC
I2C_SDA
V_EN
VCC
V_DATA[0]
V_DATA[1]
VCC
V_DATA[2]
VCC
V_DATA[3]
V_DATA[4]
V_DATA[5]
ID
UNC V
CCI
O
R
/W
RE
CO
_
E
N
V
CC
V
CCI
O
RE
G
[4
]
V
CC
RE
G
[3
]
RE
G
[2
]
V
CCI
O
V
CC
RE
G
[1
]
RE
G
[0
]
V
CC
V
CCI
O
V
_
CL
K
V
CCI
O
V
CC
V
_F
V
V
CC
V
_L
V
V
_
D
A
T
A
[7
]
V
_
D
A
T
A
[6
]
D
A
T
A[
6
]
V
CCI
O
D
A
T
A[
7
]
V
CCI
O
D
A
T
A[
8
]
D
A
T
A[
9
]
V
CCI
O
V
CC
D
A
T
A[
1
0
]
V
CC
V
CCI
O
D
A
T
A[
1
1
]
D
A
T
A[
1
2
]
V
CC
G
ND
D
A
T
A[
1
3
]
V
CC
D
A
T
A[
1
4
]
V
CC
D
A
T
A[
1
5
]
C
A
T
_
V
AL
B_
BS
Y
V
CC
S
_
CHI
P
R
SVD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
100
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
100
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
100
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
DATA[5]
VCCIO
DATA[4]
VCC
VCCIO
VCC
DATA[3]
VCCIO
DATA[2]
VCC
DATA[1]
VCCIO
DATA[0]
DCO
VCC
VCC
VCCIO
DIST_VAL
GND
VCC
VCC
VCCIO
DS
RDY
VCCIO
DATA[5]
VCCIO
DATA[4]
VCC
VCCIO
VCC
DATA[3]
VCCIO
DATA[2]
VCC
DATA[1]
VCCIO
DATA[0]
DCO
VCC
VCC
VCCIO
DIST_VAL
GND
VCC
VCC
VCCIO
DS
RDY
VCCIO
RSVD
VCCIO
G_RESET
VCC
I2C_EN
STANDBY
VCCIO
G_CLK
VCCIO
I2C_SCK
VCC
VCCIO
DCI
VCC
I2C_SDA
V_EN
VCC
V_DATA[0]
V_DATA[1]
VCC
V_DATA[2]
VCC
V_DATA[3]
V_DATA[4]
V_DATA[5]
RSVD
VCCIO
G_RESET
VCC
I2C_EN
STANDBY
VCCIO
G_CLK
VCCIO
I2C_SCK
VCC
VCCIO
DCI
VCC
I2C_SDA
V_EN
VCC
V_DATA[0]
V_DATA[1]
VCC
V_DATA[2]
VCC
V_DATA[3]
V_DATA[4]
V_DATA[5]
ID UNC
V
CCI
O
R
/W
RE
CO
_
E
N
V
CC
V
CCI
O
RE
G
[4
]
V
CC
RE
G
[3
]
RE
G
[2
]
V
CCI
O
V
CC
RE
G
[1
]
RE
G
[0
]
V
CC
V
CCI
O
V
_
CL
K
V
CCI
O
V
CC
V
_F
V
V
CC
V
_L
V
V
_
D
A
T
A
[7
]
V
_
D
A
T
A
[6
]
ID UNC
V
CCI
O
R
/W
RE
CO
_
E
N
V
CC
V
CCI
O
RE
G
[4
]
V
CC
RE
G
[3
]
RE
G
[2
]
V
CCI
O
V
CC
RE
G
[1
]
RE
G
[0
]
V
CC
V
CCI
O
V
_
CL
K
V
CCI
O
V
CC
V
_F
V
V
CC
V
_L
V
V
_
D
A
T
A
[7
]
V
_
D
A
T
A
[6
]
D
A
T
A[
6
]
V
CCI
O
D
A
T
A[
7
]
V
CCI
O
D
A
T
A[
8
]
D
A
T
A[
9
]
V
CCI
O
V
CC
D
A
T
A[
1
0
]
V
CC
V
CCI
O
D
A
T
A[
1
1
]
D
A
T
A[
1
2
]
V
CC
G
ND
D
A
T
A[
1
3
]
V
CC
D
A
T
A[
1
4
]
V
CC
D
A
T
A[
1
5
]
C
A
T
_
V
AL
B_
BS
Y
V
CC
S
_
CHI
P
R
SVD
D
A
T
A[
6
]
V
CCI
O
D
A
T
A[
7
]
V
CCI
O
D
A
T
A[
8
]
D
A
T
A[
9
]
V
CCI
O
V
CC
D
A
T
A[
1
0
]
V
CC
V
CCI
O
D
A
T
A[
1
1
]
D
A
T
A[
1
2
]
V
CC
G
ND
D
A
T
A[
1
3
]
V
CC
D
A
T
A[
1
4
]
V
CC
D
A
T
A[
1
5
]
C
A
T
_
V
AL
B_
BS
Y
V
CC
S
_
CHI
P
R
SVD