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CMT2300A

8. User Register

CMT2300A is configured by writing in the registers. The register details are listed in the below table.

Table 21. CMT2300A Register Table

Addr
R/W

Addr

R/W

Name

CUS_CMT1

CUS_CMT2

CUS_CMT3

CUS_CMT4

CUS_CMT5

CUS_CMT6

CUS_CMT7

CUS_CMT8

CUS_CMT9

CUS_CMT10

CUS_CMT11

CUS_RSSI

Name

CUS_SYS1

CUS_SYS2

CUS_SYS3

CUS_SYS4

CUS_SYS5

CUS_SYS6

CUS_SYS7

CUS_SYS8

CUS_SYS9

CUS_SYS10

CUS_SYS11

CUS_SYS12

Name

CUS_RF1

CUS_RF2

CUS_RF3

CUS_RF4

CUS_RF5

CUS_RF6

CUS_RF7

CUS_RF8

Name

CUS_RF9

CUS_RF10

CUS_RF11

CUS_RF12

CUS_FSK1

CUS_FSK2

CUS_FSK3

CUS_FSK4

CUS_FSK5

CUS_FSK6

CUS_FSK7

CUS_CDR1

CUS_CDR2

CUS_CDR3

CUS_CDR4

CUS_AGC1

CUS_AGC2

CUS_AGC3

CUS_AGC4

CUS_OOK1

CUS_OOK2

CUS_OOK3

CUS_OOK4

CUS_OOK5

Name

CUS_PKT1

CUS_PKT2

CUS_PKT3

CUS_PKT4

CUS_PKT5

CUS_PKT6

CUS_PKT7

CUS_PKT8

CUS_PKT9

CUS_PKT10

CUS_PKT11

CUS_PKT12

CUS_PKT13

CUS_PKT14

CUS_PKT15

CUS_PKT16

CUS_PKT17

CUS_PKT18

CUS_PKT19

CUS_PKT20

CUS_PKT21

CUS_PKT22

CUS_PKT23

CUS_PKT24

CUS_PKT25

CUS_PKT26

CUS_PKT27

CUS_PKT28

CUS_PKT29

Name

CUS_TX1

CUS_TX2

CUS_TX3

CUS_TX4

CUS_TX5

CUS_TX6

CUS_TX7

CUS_TX8

CUS_TX9

CUS_TX10

CUS_LBD

Name

CUS_MODE_CTL

CUS_MODE_STA

CUS_EN_CTL

CUS_FREQ_CHNL

CUS_FREQ_OFS

CUS_IO_SEL

CUS_INT1_CTL

CUS_INT2_CTL

CUS_INT_EN

CUS_FIFO_CTL

CUS_INT_CLR1

Name

CUS_INT_CLR2

CUS_FIFO_CLR

CUS_INT_FLAG

CUS_FIFO_FLAG

CUS_RSSI_CODE

CUS_RSSI_DBM

CUS_LBD_RESULT

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Function

0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B

RW
RW

User does not need to understand the details, just directly export the register contents from the RFPDK

CMT Bank

Addr

R/W

Bit 7

Bit 6

LFOSC_CAL1_EN

Bit 5

Bit 4

Bit 3

RX_TIMER_EN

Bit 2

TX_DC_EN

Bit 1

RX_DC_EN

Bit 0

DC_PAUSE

Function

0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17

RW
RW

LMT_VTR [1:0]

LFOSC_RECAL_EN

SLEEP_BYPASS_EN

MIXER_BIAS [1:0]

LNA_MODE [1:0]

SLEEP_TIMER_EN

TX_EXIT_STATE [1:0]

LNA_BIAS [1:0]

LFOSC_CAL2_EN

XTAL_STB_TIME [2:0]

RX_EXIT_STATE [1:0]

SLEEP_TIMER_M
[7:0]

SLEEP_TIMER_M

[10:8]

SLEEP_TIMER_R [3:0]

RX_TIMER_T1_M

[7:0]

RX_TIMER_T1_M

[10:8]

RX_TIMER_T1_R [3:0]

System Bank

RX_TIMER_T2_M

[7:0]

COL_DET_EN

PJD_TH_SEL

COL_OFS_SEL

RX_TIMER_T2_M

[10:8]
RX_AUTO_EXIT_DIS

DOUT_MUTE

CCA_INT_SEL [1:0]

RSSI_DET_SEL [1:0]

PJD_WIN_SEL [1:0]

RX_TIMER_T2_R [3:0]

RX_EXTEND_MODE [3:0]

RSSI_AVG_MODE
[2:0]

CLKOUT_DIV [4:0]

Addr
R/W

Bit 7

Bit 6

CLKOUT_EN

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Function

0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F

Addr

0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37

RW
RW

R/W

User does not need to understand the details, just directly export the register contents from the RFPDK

Frequency Bank

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Function

User does not need to understand the details, just directly export the register contents from the RFPDK

Data Rate Bank

Addr R/W

Bit 7

Bit 6

Bit 5

RX_PREAM_SIZE [4:0]

Bit 4

Bit 3

Bit 2

PREAM_LENG_UNIT

Bit 1

Bit 0

Function

0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54

RW
RW

DATA_MODE [1:0]

TX_PREAM_SIZE [7:0]

TX_PREAM_SIZE
[15:8]

PREAM_VALUE [7:0]

RESV

SYNC_TOL [2:0]

SYNC_SIZE [2:0]

SYNC_MAN_EN

SYNC_VALUE [7:0]

SYNC_VALUE [15:8]

SYNC_VALUE [23:16]
SYNC_VALUE [31:24]
SYNC_VALUE [39:32]
SYNC_VALUE [47:40]

RESV

PAYLOAD_LENG

[10:8]

SYNC_VALUE [63:56]

AUTO_ACK_EN

PAYLOAD_LENG [7:0]

NODE_ERR_MASK

NODE_VALUE [7:0]

NODE_VALUE [15:8]

NODE_VALUE [23:16]
NODE_VALUE [31:24]

NODE_LENG_POS_SEL

PAYLOAD_BIT_ORDER

PKT_TYPE

Baseband Bank

RESV

NODE_FREE_EN

NODE_SIZE [1:0]

NODE_DET_MODE
[1:0]

FEC_TYPE

FEC_EN

CRC_BYTE_SWAP

CRC_BIT_INV

CRC_RANGE

CRC_TYPE [1:0]

CRC_EN

CRC_BIT_ORDER

WHITEN_SEED [8]

WHITEN_SEED_TYPE

CRC_SEED [7:0]

CRC_SEED [15:8]

WHITEN_TYPE [1:0]

WHITEN_SEED [7:0]

WHITEN_EN

MANCH_TYPE

MANCH_EN

RESV

TX_PREFIX_TYPE
[1:0]

FIFO_AUTO_RES_EN

Bit 7

Bit 6

Bit 5

TX_PKT_NUM [7:0]

TX_PKT_GAP [7:0]

FIFO_TH [6:0]

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Function

0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F

RW
RW

User does not need to understand the details, just directly export the register contents from the RFPDK

TX Bank

Addr
R/W

Bit 7

RESV

Bit 6

RESV

Bit 5

RSTN_IN_EN

LOCKING_EN

Bit 4

Bit 3

CHIP_MODE_SWT [7:0]

Bit 2

Bit 1

Bit 0

Function

0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A

CFG_RETAIN

RESV

CHIP_MODE_STA [3:0]

RESV

FH_CHANNEL [7:0]

FH_OFFSET [7:0]

Addr
R/W

RESV

RF_SWT1_EN

RESV

SL_TMO_EN

TX_DIN_EN

RESV

Bit 7

RESV

LBD_FLG

RESV

RF_SWT2_EN

LFOSC_OUT_EN

RX_TMO_EN

TX_DIN_SEL [1:0]

RESV

Bit 6

RESV

COL_ERR_FLG

GPIO3_SEL [1:0]

GPIO2_SEL [1:0]

GPIO1_SEL [1:0]

Control Bank 1

INT_POLAR

TX_DIN_INV

TX_DONE_EN

SL_TMO_FLG

Bit 5

LBD_CLR

RESV

PKT_ERR_FLG

RX_FIFO_FULL_FLG

RX_FIFO_NMTY_FLG

INT1_SEL [4:0]
INT2_SEL [4:0]

PREAM_OK_EN

SYNC_OK_EN

NODE_OK_EN

CRC_OK_EN

FIFO_AUTO_CLR_DIS

FIFO_TX_RD_EN

FIFO_RX_TX_SEL

FIFO_MERGE_EN

RX_TMO_FLG

TX_DONE_FLG

TX_DONE_CLR

SL_TMO_CLR

Bit 4

Bit 3

Bit 2

Bit 1

PREAM_OK_CLR

SYNC_OK_CLR

NODE_OK_CLR

CRC_OK_CLR

RESV

FIFO_RESTORE

FIFO_CLR_RX

PREAM_OK_FLG

SYNC_OK_FLG

NODE_OK_FLG

CRC_OK_FLG

RX_FIFO_TH_FLG

RX_FIFO_OVF_FLG

TX_FIFO_FULL_FLG

TX_FIFO_NMTY_FLG

PKT_DONE_EN

SPI_FIFO_RD_WR_SEL

RX_TMO_CLR

Bit 0

PKT_DONE_CLR

FIFO_CLR_TX

PKT_OK_FLG

TX_FIFO_TH_FLG

Function

0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71

Control Bank 2

RSSI_CODE [7:0]

RSSI_DBM [7:0]

LBD_RESULT [7:0]

Содержание CMT2300A-EQR

Страница 1: ...e system design Up to 20 dBmTx Power and 121 dBm sensitivity optimize the performance of the application It supports a variety of packet formats and codec methods to meet the needs of various different applications In addition CMT2300A also supports 64 byte Tx Rx FIFO GPIO and interrupt configuration Duty Cycle operation mode channel sensing high precision RSSI low voltage detection power on reset...

Страница 2: ...2 1 12 4 Sensitivity VS Temperature 13 1 12 5 Tx Power VS Supply Voltage 14 1 12 6 Tx Phase Noise 14 2 Pin Descriptions 16 3 Typical Application Schematic 18 3 1 Direct Tie Schematic Diagram 18 3 2 RF Switch Type Schematic 20 4 Function Descriptions 23 4 1 Transmitter 24 4 2 Receiver 24 4 3 Additional Functions 24 4 3 1 Power On Reset POR 24 4 3 2 Crystal Oscillator 25 4 3 3 Sleep Timer 26 4 3 4 L...

Страница 3: ...PIO and Interrupt 36 6 Packet Handler 39 6 1 Direct Mode 39 6 2 Packet Mode 40 7 Low Power Operation 42 7 1 Duty Cycle Operation Mode 42 7 2 Super low Power Rx Mode 42 7 3 Receiver Power VS Performance Configuration 43 8 User Register 44 9 Ordering Information 46 10 Packaging Information 47 11 Top Marking 48 12 Revise History 49 13 Contacts 50 ...

Страница 4: ...V Interface Voltage VIN 0 3 VDD 0 3 V Junction Temperature TJ 40 125 Storage Temperature TSTG 50 150 Soldering Temperature TSDR Lasts at least 30 seconds 255 ESD Rating 2 Human Body Model HBM 2 2 kV Latch up Current 85 100 100 mA Notes 1 Exceeding the Absolute Maximum Ratings may cause permanent damage to the equipment This value is a pressure rating and does not imply that the function of the equ...

Страница 5: ...K 915 MHz 10 kbps 10 kHz FDEV 8 9 mA RX current low power mode IRx LP FSK 433 MHz 10 kbps 10 kHz FDEV 7 2 mA FSK 868 MHz 10 kbps 10 kHz FDEV 7 3 mA FSK 915 MHz 10 kbps 10 kHz FDEV 7 6 mA TX current ITx FSK 433 MHz 20 dBm Direct Tie 72 mA FSK 433 MHz 20 dBm RF switch 77 mA FSK 433 MHz 13 dBm Direct Tie 23 mA FSK 433 MHz 10 dBm Direct Tie 18 mA FSK 433 MHz 10 dBm Direct Tie 8 mA FSK 868 MHz 20 dBm D...

Страница 6: ...m DR 20 kbps FDEV 20 kHz Low power setting 109 dBm DR 50 kbps FDEV 25 kHz 108 dBm DR 100 kbps FDEV 50 kHz 105 dBm DR 200 kbps FDEV 100 kHz 102 dBm DR 300 kbps FDEV 100 kHz 99 dBm Sensitivity 915 MHz S915 HP DR 2 0 kbps FDEV 10 kHz 117 dBm DR 10 kbps FDEV 10 kHz 113 dBm DR 10 kbps FDEV 10 kHz Low power mode 111 dBm DR 20 kbps FDEV 20 kHz 111 dBm DR 20 kbps FDEV 20 kHz Low power mode 109 dBm DR 50 k...

Страница 7: ...IRange RSSI 120 20 dBm More Sensitivity Typical Configuration 433 92 MHz DR 1 2kbps FDEV 5 kHz 122 9 dBm 433 92 MHz DR 1 2kbps FDEV 10 kHz 121 8 dBm 433 92 MHz DR 1 2kbps FDEV 20 kHz 119 5 dBm 433 92 MHz DR 2 4kbps FDEV 5 kHz 120 6 dBm 433 92 MHz DR 2 4kbps FDEV 10 kHz 120 3 dBm 433 92 MHz DR 2 4kbps FDEV 20 kHz 119 7 dBm 433 92 MHz DR 9 6 kbps FDEV 9 6 kHz 116 0 dBm 433 92 MHz DR 9 6 kbps FDEV 19...

Страница 8: ... Harmonic output for FRF 433 MHz 1 H2433 2nd harmonic 13 dBm POUT 52 dBm H3433 3nd harmonic 13 dBm POUT 52 dBm Harmonic output for FRF 868 MHz 1 H2868 2nd harmonic 13 dBm POUT 52 dBm H3868 3nd harmonic 13 dBm POUT 52 dBm Harmonic output for FRF 915 MHz 1 H2868 2nd harmonic 13 dBm POUT 52 dBm H3868 3nd harmonic 13 dBm POUT 52 dBm Notes 1 The harmonic parameter values mainly depend on the quality of...

Страница 9: ... Hz 100 kHz frequency deviation 99 dBc Hz 500 kHz frequency deviation 118 dBc Hz 1MHz frequency deviation 127 dBc Hz 10 MHz frequency deviation 134 dBc Hz Phase noise 868 MHz PN868 10 kHz frequency deviation 92 dBc Hz 100 kHz frequency deviation 95 dBc Hz 500 kHz frequency deviation 114 dBc Hz 1MHz frequency deviation 121 dBc Hz 10 MHz frequency deviation 130 dBc Hz Phase noise 915 MHz PN915 10 kH...

Страница 10: ...stal frequency tolerance is limited by the receiver bandwidth and the RF frequency offset between the transmitter and the receiver 3 The parameter is largely related to the crystal 1 9 Low Frequency Oscillator Table 9 Low Frequency Oscillator Specifications Parameter Symbol Condition Min Typ Max Unit Calibration frequency 1 FLPOSC 32 kHz Frequency accuracy After calibration 1 Temperature coefficie...

Страница 11: ...VIL 0 2 VDD Digital output high level VOH IOH 0 5mA Vdd 0 4 V Digital output low level VOL IOL 0 5mA 0 4 V SCLK Frequency FSCL 5 MHz SCLK high time TCH 50 ns SCLK low time TCL 50 ns SCLKrise time TCR 50 ns SCLKfall time TCF 50 ns 1 12Figures of Critical Parameters 1 12 1 Rx Current VS Supply Voltage Testing Condition Freq 434MHz 868MHz Fdev 10KHz BR 10Kbps 7 40 7 60 7 80 8 00 8 20 8 40 8 60 8 80 3...

Страница 12: ...est Condition Freq 868MHz Fdev 10KHz BR 10Kbps 1 12 3 Sensitivity VS Voltage 7 0 7 3 7 5 7 8 8 0 8 3 8 5 8 8 9 0 9 3 9 5 40 25 85 Current Consumption mA Temperature Rx Current vs Volt Temp 3 3V 1 8V 3 6V 7 0 7 3 7 5 7 8 8 0 8 3 8 5 8 8 9 0 9 3 9 5 40 25 85 Current Consumption mA Temperature Rx Current vs Volt Temp 3 3V 1 8V 3 6V ...

Страница 13: ...ure Test Condition FSK DEV 10KHz BR 10Kbps 117 5 117 0 116 5 116 0 115 5 115 0 114 5 114 0 113 5 113 0 1 8 2 1 2 4 2 8 3 0 3 3 3 6 Sensitivity dBm Supply Voltage V Sensitivity vs Voltage 434MHz 868MHz 118 0 117 0 116 0 115 0 114 0 113 0 112 0 40 25 85 Sensitivity dBm Temperature Sensitivity vs Temperature 434MHz 868MHz ...

Страница 14: ... 10 0 11 0 12 0 13 0 14 0 15 0 16 0 17 0 18 0 19 0 20 0 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 2 2 1 2 0 1 9 1 8 Tx Power dBm Supply Voltage V Tx Power vs Supply Voltage 20dBm 13dBm 9 0 10 0 11 0 12 0 13 0 14 0 15 0 16 0 17 0 18 0 19 0 20 0 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 1 2 0 1 9 1 8 Tx Power dBm Supply Voltage V Tx Power vs Supply Voltage...

Страница 15: ...42 434 92 435 42 435 92 Power dBm center 433 92MHz sweep 5s 2000pts Res BW 1kHz 433 92MHz Phase Noise output 13dBm span 4MHz att30dB 12 4dBm 100 80 60 40 20 0 20 866 866 5 867 867 5 868 868 5 869 869 5 870 Power dBm center 868MHz sweep 5s 2000pts Res BW 1kHz 868MHz Phase Noise output 13dBm span 4MHz att30dB ...

Страница 16: ...2300APin Descriptions Pin Name I O Internal IO Schematic Descriptions 1 RFIP I RF signal input P 2 RFIN I RF signal input N 3 PA O PA output 4 AVDD IO Analog VDD 5 AGND IO Analog GND 6 DGND IO Digital GND 7 DVDD IO Digital VDD 8 1 GPIO3 IO GPIO3 din pd_din dout pd_dout Data tristate pd_din default value is 1 pd_dout default value is 0 VDD Configured as CLKO DOUT DIN INT2 and DCLK TX RX 9 SCLK I SC...

Страница 17: ...t 14 XO O Crystal circuit output 15 1 GPIO2 IO GPIO2 din pd_din dout pd_dout Data tristate pd_din default value is 1 pd_dout default value is 0 VDD Configured as INT1 INT2 DOUT DIN DCLK TX RX and RF_SWT 16 1 GPIO1 IO GPIO1 din pd_din dout pd_dout Data tristate pd_din default value is 1 pd_dout default value is 0 VDD Configured as DOUT DIN INT1 INT2 DCLK TX RX and RF_SWT 17 GND I Analog GND It must...

Страница 18: ... 2 2 2 pF C8 5 0603 NP0 50 V 4 7 uF C9 5 0603 NP0 50 V 470 pF C10 5 0603 NP0 50 V 0 1 uF C11 5 0603 NP0 50 V 0 1 uF L1 5 0603 Multilayer chip inductor 180 100 100 nH Sunlord SDCL L2 5 0603 Multilayer chip inductor 56 10 8 2 nH Sunlord SDCL L3 5 0603 Multilayer chip inductor 39 8 2 6 8 nH Sunlord SDCL L4 5 0603 Multilayer chip inductor 18 10 8 2 nH Sunlord SDCL L5 5 0603 Multilayer chip inductor 18...

Страница 19: ... C10 5 0603 NP0 50 V 0 1 uF C11 5 0603 NP0 50 V 0 1 uF L1 5 0603 Multilayer chip inductor 180 100 100 nH Sunlord SDCL L2 5 0603 Multilayer chip inductor 22 12 12 nH Sunlord SDCL L3 5 0603 Multilayer chip inductor cap 15pF 15 15 nH Sunlord SDCL L4 5 0603 Multilayer chip inductor 33 6 2 6 2 nH Sunlord SDCL L5 5 0603 Multilayer chip inductor 33 6 2 6 2 nH Sunlord SDCL L6 5 0603 Multilayer chip induct...

Страница 20: ...www cmostek com Rev1 0a 20 50 CMT2300A 3 2 RF Switch Type Schematic Figure 3 Application Schematic Diagram for RF Switch Type ...

Страница 21: ... 24 24 pF C17 5 0402 NP0 50 V 10 10 pF C18 5 0402 NP0 50 V 10 10 pF C19 5 0402 NP0 50 V 27 pF C20 5 0402 NP0 50 V 27 pF C21 5 0402 NP0 50 V 27 pF C22 5 0402 NP0 50 V 27 pF L1 5 0603 Multilayer chip inductor 180 100 nH Sunlord SDCL L2 5 0402 Multilayer chip inductor 27 6 8 nH Sunlord SDCL L3 5 0402 Multilayer chip inductor 18 12 nH Sunlord SDCL L4 5 0402 Multilayer chip inductor 33 22 nH Sunlord SD...

Страница 22: ...layer chip inductor 33 22 nH Sunlord SDCL L5 5 0402 Multilayer chip inductor 15 10 nH Sunlord SDCL L6 5 0402 Multilayer chip inductor 27 12 nH Sunlord SDCL L7 5 0402 Multilayer chip inductor 27 12 nH Sunlord SDCL L8 5 0402 Multilayer chip inductor 68 18 nH Sunlord SDCL Y1 10 ppm SMD32 25 mm 26 MHz EPSON U1 CMT2300A Ultra Low Power Sub 1GHz RF Transceiver CMOSTEK U2 AS179 PHEMT GaAs IC SPDT Switch ...

Страница 23: ... circuit mixes the RF signal to IF and converts the signal from analog to digital through the Limiter module then outputs I Q two single bit signals to the digital circuit for G FSK demodulation At the same time SARADC will convert the real time RSSI signal to 8 bit digital signal and sent them to the digital part for OOK demodulation and other processing The digital circuit is responsible for mix...

Страница 24: ... package elements 4 2 Receiver CMT2300A has a built in ultra low power high performance low IF OOK FSK receiver The RF signal induced by the antenna is amplified by a low noise amplifier and is converted to an intermediate frequency by an orthogonal mixer The signal is filtered by the image rejection filter and is amplified by the limiting amplifier and then sent to the digital domain for digital ...

Страница 25: ...tion of POR 4 3 2Crystal Oscillator The crystal oscillator provides a reference clock for the phase locked loop as well as a system clock for the digital circuits The value of load capacitance depends on the crystal specified CL parameters The total load capacitance between XI and XO should be equal to CL in order to make the crystal accurately oscillate at 26 MHz C15 and C16 are the load capacita...

Страница 26: ...rithmic amplifier of I channels and Q channel contains the received signal indicator in which the DC voltage is generated is proportional to the input signal strength The output of RSSI is the sum of the values of the two channels signals The output has 80dB dynamic range above the sensitivity After the RSSI output is sampled by the ADC and filtered by a SAR FILTER and a RSSI AVG FILTER The order ...

Страница 27: ...1 otherwise outputs logic 0 The output can be used as a source of the RSSI VLD interrupt or the receive time extending condition in the super low power SLP mode In direct data mode by setting the DOUT_MUTE register bit to 1 the PJD can mute the FSK demodulated data output while there is not wanted signal received The PJD technique is similar to the traditional carrier sense technique but more reli...

Страница 28: ...een them The system can withstand up to 15 6 or symbol rate error Other similar products in the industry cannot reach this level 3 MANCHESTER system This system evolves from the COUNTING system The basic feature is the same The only difference is that the system is specially designed for Manchester codec Special processing can be done when the TX symbol rate has unexpected changes 4 3 9 Fast Frequ...

Страница 29: ...east half a SCL cycle and then send the R W bit After the MCU sends out the last falling edge of SCLK it must wait for at least half a SCLK cycle and then pull the CSB high To be noticed when reading a register MCU and CMT2300A will have to switch the direction of their IO SDIO between the address bit 0 and the data bit 7 It is required that the MCU switches the IO to input mode before send out th...

Страница 30: ...X and RX By configuring the FIFO_RX_TX_SEL to indicate whether it is currently used as TX FIFO or RX FIFO When the two FIFO are not merged users can fill in the TX FIFO while the RX FIFO is used to receive data in the RX mode The FIFO can be accessed via the SPI interface The user can clear the FIFO by setting FIFO_CLR_TXor FIFO_CLR_RX to 1 Also the user can re send the old data in the TX FIFO by ...

Страница 31: ...o the FIFO FCSB must be pulled down 1 clock cycle at first and then send the rising edge of SCL After the last falling edge of SCL is sent the MCU must wait at least 2 us to pull up the FCSB Between the adjacent read write operations the FCSB must be pulled high for 4us at least When writing the FIFO the first bit data must be ready 0 5 clock cycles before sending the first rising edge of SCL SCLK...

Страница 32: ...0 3 2 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 21 20 23 22 25 24 27 26 29 28 31 30 RX DATA Noise Noise SYNC_OK RX FIFO ARRAY RX_FIFO_OVF FIFO_TH 16 RX_FIFO_WBYTE Figure 13 CMT2300ARX FIFO interrupt timing diagram 1 0 3 2 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 21 20 23 22 25 24 27 26 29 28 31 30 EMPTY FULL TX_FIFO_NMTY TX_FIFO_TH TX_FIFO_FULL Sync 1 0 3 2 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 ...

Страница 33: ...0 afterword it has to be longer than the crystal inherent settling time The chip stays in IDLE state until the crystal is settled After the crystal is settled the chip perform calibration of each module and stay in SLEEP state after then to wait for initialization configuration by user The chip will back to IDLE state and redo startup steps upon reset at anytime POR VDD POR Release 1 ms XTAL Stabl...

Страница 34: ...1 TX 0110 go_stby go_tx go_stby go_sleep go_stby go_rx go_switch go_switch g o _ s t b y g o _ t f s g o _ s t b y g o _ r f s go_tfs go_tx go_rfs go_rx go_tfs go_sleep go_rfs go_sleep go_sleep go_tx go_sleep go_rx Power up Figure 16 State Switch Diagram SLEEP State The chip power consumption is the lowest in SLEEP state and almost all the modules are turned off SPI is open the registers of the co...

Страница 35: ...le is off the other modules are turned on and the current will be larger than STBY Because PLL has been locked in the TX frequency TFS cannot switch to RX Switching from STBY to TFS probably requires PLL calibration and stability time of 350us Switching from SLEEP to TFS needs to add the crystal start up and settled time Switching from other state to TFS will be completed immediately RX State All ...

Страница 36: ...300A has 2 interrupt ports They can be configured to different GPIO outputs Pin No Name I O Function 16 GPIO1 IO Configured as DOUT DIN INT1 INT2 DCLK TX RX RF_SWT 15 GPIO2 IO Configured as INT1 INT2 DOUT DIN DCLK TX RX RF_SWT 8 GPIO3 IO Configured as CLKO DOUT DIN INT2 DCLK TX RX Interrupt mapping table is as below INT1 and INT2 mapping is the same Take INT1 as an example ...

Страница 37: ...e is written to the RX FIFO Itis a pulse Auto RX_FIFO_OVF 01111 indicates RX FIFO is overflow Auto TX_FIFO_NMTY 10000 Indicates that TX FIFO is not empty Auto TX_FIFO_TH 10001 Indicates the number of unread bytes of the TX FIFO is over FIFO TH Auto TX_FIFO_FULL 10010 Indicates TX FIFO is full Auto STATE_IS_STBY 10011 Indicates that the current state is STBY Auto STATE_IS_FS 10100 Indicates that th...

Страница 38: ...GPO1_SEL 1 0 GPIO1 0 Preamble OK Interrupt Source 0 Sycn Word OK Interrupt Source 0 Node ID OK Interrupt Source 0 CRC OK Interrupt Source 0 Packet OK Interrupt Source 0 Sleep Timeout Interrupt Source 0 Receive Timeout Interrupt Source INT1_CTL 4 0 RX_ACTIVE 0 RSSI_VLD_FLG 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 其它 STATE_IS_FS STATE_IS_RX RX_ACTIVE D Q 0 1 PKT_DONE_FLG PKT_DONE_...

Страница 39: ...or 3 The typicalRX direct mode control sequence for the MCU is 1 Configures GPIOsusing theCUS_IO_SEL register 2 Configures DATA_MODE 0 3 Send the go_rx command 4 Capture the data from DOUT continuously 5 Send the go_sleep go_stby go_rfs command to stop receiving and save the power Tx processing In the direct mode the data to be transmitted is sent directly to the chip from the external MCU by via ...

Страница 40: ...Length in front of the Node ID variable packet format Length in the back of the Node ID and fixed packet format Each element in the packet supports flexible configurations as shown below Preamble Sync Word Length Node ID Data CRC Payload CRC 1 2 3 4 5 6 Manchester Whiten FEC 7 4 Manchester Data Only CRC Figure 20 Variable length packet Length in front of Node ID Preamble Sync Word Length Node ID D...

Страница 41: ...e go_sleep go_stby go_rfs command to stop the receiving and save the power 6 Clears the packet interrupts using CUS_ INT_CLR1 and CUS_INT_CLR2 registers Tx processing In the packet mode MCU can fill the data in the FIFO in advance in the STBY and TFS state or fill them in the FIFO while the chip sends the data or use the combination of the above two methods The typical Txpacket mode control sequen...

Страница 42: ...upon different application requirements All these options are available only when RX_TIMER_EN is set as 1 namely Rx counter is active The core function of SLP Rx is to reduce Rx time to the best during no signal period meanwhile properly extend Rx time during signal existing time then to reach stable Rx with minimum power consumption In general traditional short range wireless transceiver systems ...

Страница 43: ..._OK is valid 9 Any one of PREAM_OK or NODE_OK is valid 10 Any one of PREAM_OK or SYNC_OK or NODE_OK is valid 11 Once meet the Rx extended condition during T1 switch to T2 Leave T2 and pass the control authority to MCU as soon as SYNC is detected otherwise exit Rx when T2 timed out RSSI_VLD is valid 12 PREAM_OK is valid 13 RSSI_VLD and PREAM_OK are valid simultaneously The T1 and T2 mentioned in th...

Страница 44: ...ed to understand the details just directly export the register contents from the RFPDK Frequency Bank Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function User does not need to understand the details just directly export the register contents from the RFPDK Data Rate Bank Addr R W Bit 7 Bit 6 Bit 5 RX_PREAM_SIZE 4 0 Bit 4 Bit 3 Bit 2 PREAM_LENG_UNIT Bit 1 Bit 0 Function 0x38 0x39 0x3A 0x3B 0x3...

Страница 45: ...deviation and power 0x60 0x6A Control Bank 1 Set by MCU in application not generated by RFPDK To setup chip working state frequency hopping GPIOs and interrupts control 0x6B 0x71 Control Bank 1 Set by MCU in application not generated by RFPDK To read interrupt flags and RSSI value control the FIFO To simplify the operation users should firstly setup all the desired parameters on the RFPDK export t...

Страница 46: ...r Sub 1GHz RF Transceiver QFN16 3x3 Tape Reel 1 8 to 3 6V 40 to 85 3 000 Notes 1 E represents extended industrial grade The temperature range is from 40 to 85 Q represents QFN16 packaging R represents tape reel packing MOQ is 3000pcs For more information about product please visit www cmostek com For purchasing or price requirements please contact sales cmostek com or local sales representative ...

Страница 47: ...ackaging information is as below D2 E2 b e L D E A A1 c Top View Bottom View Side View 1 1 16 16 Figure 24 16 Pin QFN 3x3 packaging Table 24 16 Pin QFN 3x3 packaging Symbol Size mm Min Max A 0 7 0 8 A1 0 05 b 0 18 0 30 c 0 18 0 25 D 2 90 3 10 D2 1 55 1 75 e 0 50 BSC E 2 90 3 10 E2 1 55 1 75 L 0 35 0 45 ...

Страница 48: ...ng description Marking method Laser Pin 1 mark Circle diameter 0 3 mm Font size 0 5 mm right aligned Line 1 marking 300A represents model CMT2300A Line 2 marking represents the internal tracking coding Line 3 marking Date code is assigned by assembly factory Y represents the last digit of the year WW represents working week ...

Страница 49: ...015 08 06 0 7 All Initial release for production version 2017 03 22 0 8 All Changed T R to 3 000 pcs Added AN document list Added new RF parameters and curves 2017 08 10 0 9 All Added and changed some performance numbers Changed RSSI descriptions Added POR descriptions Added PJD AFC and CDR descriptions Added receiver Power VS Performance descriptions Changed some characters and figures Detected t...

Страница 50: ...med for inaccuracies and specifications within this document are subject to change without notice The material contained herein is the exclusive property of CMOSTEK and shall not be distributed reproduced or disclosed in whole or in part without prior written permission of CMOSTEK CMOSTEK products are not authorized for use as critical components in life support devices or systems without express ...

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