Configuring Cisco Multimode G.SHDSL EFM/ATM in Cisco ISR G2
Troubleshooting Cisco G.SHDSL EFM/ATM
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Configuring Cisco Multimode G.SHDSL EFM/ATM in Cisco ISR G2
Control Register (0x8210):
MAC Enable 1 Short Packet Padding 1
Loopback Mode 0 TXCRC Gen 1
Latency Register: (0xFFFE)
Tx FIFO MAX Packet Count : 31
Tx FIFO MAX Byte Count : 2046
Congestion Management Info:
tx-ring-limit: 64, high water_mark: 64, low water_mark: 60
Congestion Notification Register: (0x8000)
Queue Id : 0
Queue Status : Below low watermark
Status Register (0x0004):
TX MAC pause 0 RX MAC pause 0
MAC110 Frame statistics registers
---------------------------------
Egress frame counters:
----------------------
Frame Count 9
Byte Count 729
Abort Count 0
Tx64 Bytes Packet Count0
Tx65_to_127 Bytes Packet Count9
Tx128_to_255 Bytes Packet Count0
Tx256_to_511 Bytes Packet Count 0
Tx512_to_1023 Bytes Packet Count 0
Tx1024_to_1518 Bytes Packet Count 0
TxUndersize Packet Count 0
TxOversize Packet Count 0
Ingress frame counters:
--------------------------
Frame Count 8
Byte Count 648
Multicast Filt Drops 8
Multicast Frames 8
CRC Error Count 0
Congestion Drop Count 0
Oversize Drop Count 0
Pause Frame Count 0
Rx64 bytes Packet Count 0
Rx65_to_127 bytes Packet Count 8
Rx128_to_255 bytes Packet Count 0
Rx256_to_511 bytes Packet Count 0
Rx512_to_1023 bytes Packet Count 0
Rx1024_to_1518 bytes Packet Count 0
RxUndersize Packet Count 0
RxOversize Packet Count 0
******* HWIC Host Registers at ECFEC000 *******
Status (0x00):
Card Present Low 0 Graceful Stop Tx Complete 0
Config (0x0000360E):
Hwic Reset 0 Hwic Host Reset 0
Hwic DDR Bus 50MHZ Enable 0 Hwic EHWIC Mode Enable 1
Hwic IRQ2 Type Mgmt Hwic IRQ1 Type Err
Rx Queue Watermark Enable 0 Auto XOFF When Full 0
Rx Int On Last 0 Graceful Stop Tx 0
Generic Rx Enable 1 Generic Tx Enable 1
DDR Enable 1 Loopback 0
Error Interrupt Enable (0x20D7E):