Cirrus Logic CRD5378, Руководство пользователя

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CRD5378
DS639RD2 5
3.4.8 Plot Error ............................................................................................................. 43
3.5 Control Panel ................................................................................................................... 44
3.5.1 DF Registers ....................................................................................................... 45
3.5.2 DF Commands .................................................................................................... 45
3.5.3 SPI ...................................................................................................................... 45
3.5.4 Macros ................................................................................................................ 46
3.5.5 GPIO ................................................................................................................... 46
3.5.6 Customize ........................................................................................................... 47
3.5.7 External Macros .................................................................................................. 47
4. BILL OF MATERIALS ........................................................................................................... 48
5. LAYER PLOTS ...................................................................................................................... 49
6. SCHEMATICS ....................................................................................................................... 57
LIST OF FIGURES
Figure 1. CRD5378 Block Diagram............................................................................................... 12
Figure 2. Differential Pair Routing ................................................................................................. 29
Figure 3. Quad Group Routing...................................................................................................... 29
Figure 4. Bypass Capacitor Placement......................................................................................... 30
LIST OF TABLES
Table 1. Amplifier Pin 13 Jumper Setting........................................................................................ 7
Table 2. System Clock Input Setting ............................................................................................... 7
Table 3. CS5378 PLL Mode Select Setting (R15, R41, R42) ......................................................... 7
Table 4. Input SYNC Source Selection Setting............................................................................... 7
Table 5. CS5378 SYNC Source Selection Setting.......................................................................... 7
Table 6. Pin Header Input Connections ........................................................................................ 13
Table 7. Amplifier Pin 13 Resistor Settings................................................................................... 16