Cirrus Logic CDB48500-USB, Руководство пользователя, Страница: 37 / 52

A-3
©
Copyright 2008 Cirrus Logic , Inc. DS784DB1
Introduction
CDB48500--USB Evaluation Kit Guide
The CDB USB MASTER drives the serial host control port and CS8416_RESET signals on this page.
The RCA jack for coaxial S/PDIF input and optical jack for optical S/PDIF input is listed on this page too.
A.1.1.1.6 Codec #1(CS42448) (See Figure A-6 )
The CS42448 is a multi-channel ADC/DAC that is capable of simultaneously supporting up to 6 channels
of analog input and 8 channels analog output. This is one of the two CODEC.
The serial host control port (SCL/CCLK, SDA/CDOUT, AD1/CDIN, AD0/CS) shares clock and data lines
with the CS485XX and CS8416. Both CODECS share the CS42448_CS line to this chip and driven only
when in SPI mode. The pull-ups required for the SCL and SDA pins are shared with the other devices on
the CDB48500 board.
The CS42448_RST signal is a dedicated reset signal driven by a general-purpose output of the CS8416.
The CS42448 is a slave to the MUXED_MCLK signal, which is the master audio clock for the entire
CDB48500 system.
The CS42448 masters the CS8416_SCLK and CS8416_LRCLK signals which are used to shift I
2
S data
out of the CS42448 and shift I
2
S data into the CS485XX when ADC is used as the data input for the DSP.
The CS42448 slaves to the DSP_SCLK and DSP_LRCLK signals which are used to shift I
2
S data out of
the CS485XX and shift I
2
S data into the CS42448.
The analog inputs and outputs of the CS42448 are being used in single-ended mode. This is evident
when looking at the input and output filter circuitry on page 6 of the schematics.
AIN5 of the CS42448 has an internal analog multiplexer that can be used to select between single-ended
inputs on the AIN5+ and AIN5- pins. This feature is used to share AIN5 between the microphone input
and RCA jack J5.
The transistor connected to MUTEC (Q1) provides the current drive necessary to drive all of the mute
transistors (see page 9 of schematic) into saturation.
The CDB USB MASTER drives the serial host control port signals on this page.
A.1.1.1.7 Codec #2 (CS42448) (See Figure A-7 )
The CS42448 is a multi-channel ADC/DAC that is capable of simultaneously supporting up to 6 channels
of analog input and 8 channels analog output. This is one of the two CODEC.
The serial host control port (SCL/CCLK, SDA/CDOUT, AD1/CDIN, AD0/CS) shares clock and data lines
with the CS485XX and CS8416. Both CODECS share the CS42448_CS line to this chip and driven only
when in SPI mode. The pull-ups required for the SCL and SDA pins are shared with the other devices on
the CDB48500 board.
The CS42448_RST signal is a dedicated reset signal driven by a general-purpose output of the CS8416.
The CS42448 is a slave to the MUXED_MCLK signal, which is the master audio clock for the entire
CDB48500 system.
The CS42448 masters the CS8416_SCLK and CS8416_LRCLK signals which are used to shift I
2
S data
out of the CS42448 and shift I
2
S data into the CS485XX when ADC is used as the data input for the DSP.
The CS42448 slaves to the DSP_SCLK and DSP_LRCLK signals which are used to shift I
2
S data out of
the CS485XX and shift I
2
S data into the CS42448.