Cirrus Logic CDB48500-USB, Руководство пользователя, Страница: 36 / 52

A-2
©
Copyright 2008 Cirrus Logic , Inc. DS784DB1
Introduction
CDB48500--USB Evaluation Kit Guide
and audio CODEC (CS42448); as well as changing clock modes. This multiplexer defaults to choose the
on-board audio sources. The CDB USB MASTER CARD audio delivery interface is currently under
development.
The input and output audio clocking domains are separated. This allows the DSP to accept audio in one
Fs and produce output samples at a different sample rate such as 2Fs or 4Fs. The CS485XX is slave only
on the input clock domain (MUXED_SCLK, MUXED_LRCLK). On the audio outputs, the CS485XX is
slave-only for the MUXED_MCLK master audio clock, and master-only for DSP_SCLK and DSP_LRCLK
which are used to shift data out of the CS485XX.
The CDB USB MASTER USB board acts as the host controller in the CDB48500 platform, and is
connected to the CDB48500 via J11 on page 11 of the schematics. The CDB USB MASTER drives
several DSP interfaces including the serial host control port (SCP1), the debug port, and DSP_RESET.
The optical jack for S/PDIF output is listed on this page too. The S/PDIF output line also goes to the serial
data input of U5. Therefore when the S/PDIF port is enabled, noise will be heard on AOUT_4A and
AOUT_4B.
A.1.1.1.4 Serial Flash Memory (See Figure A-4 )
The CDB48500 was designed with an Atmel 4 Mbit and SST 4 Mbit serial flash on-board. However only
the SST Flash is connected to the DSP. To connect the Atmel part remove R101 and add a 0 Ohm resistor
to R110. In addition to serial flash a 512 Kb Serial I
2
C is also provided. Information on programming these
devices and booting from them can be found in the AN298MPMF.
A.1.1.1.5 S/PDIF Receiver (See Figure A-5 )
The CS8416 is a S/PDIF receiver capable of supporting sample rates up to 192 kHz.
The serial host control port (SCL/CCLK, SDA/CDOUT, AD1/CDIN, AD0/CS) shares clock and data lines
with the CS485XX and CS42448. The CS8416_CS line is unique to this chip and driven only when in SPI
mode. The pull-ups required for the SCL and SDA pins are shared with the other devices on the
CDB48500 board.
The BRD_RST signal is a shared reset signal.
The reference clock for the CS8416 is the XTAL_OUT (buffered 24.576 MHz crystal) output from the
CS485XX.
The CS8416_MCLK signal is the master audio clock for on-board audio sources. This clock can be either
an MCLK recovered from a S/PDIF stream or the XTAL_OUT reference, depending on the setting of the
CS8416’s internal multiplexer.
The CS8416 is master only for the CS8416_MCLK signal, which is one possible source for the
MUXED_MCLK master audio clock.
The CS8416 slaves to the CS8416_SCLK and CS8416_LRCLK signals which are used to shift I
2
S data
out of the CS8416 and shift I
2
S data into the CS485XX.
The CS8416 has 2 different S/PDIF inputs available to it. One is optical on one is coaxial. Refer to Section
4.2.2.1, “Audio In via S/PDIF” on page 4-3 to determine how to configure the board for optical or coaxial
input.
A general-purpose output of the CS8416 is used to generate an independent reset signal for the CS42448
audio CODEC. Providing a separate reset line for each audio device allows the system to sequence the
order in which audio devices come out of reset.