Chroma 66203, Руководство пользователя

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Using Remote Control
5-13
Event register > 0, QUES bit of the Status Byte register is set too.
Setting syntax: none
Setting parameters: none
Setting example: none
Query syntax:
STATus:QUEStionable?<PMT>
Return parameters: <NR1>, 0 ~ 65535
Header on: :STATUS:QUESTIONABLE:EVENT<space><NR1><RMT>
Header off: <NR1><RMT>
Query example: none
STATus:QUEStionable:CONDition?
Description: This query returns the value of the Questionable Condition register,
which is a read-only register that holds the real-time questionable
status of the Power Meter.
Setting syntax: none
Setting parameters: none
Setting example: none
Query syntax:
STATus:QUEStionable:CONDition?<PMT>
Return parameters: <NR1>, 0 ~ 65535
Header on: :STATUS:QUESTIONABLE:CONDITION<space><NR1><RMT>
Header off: <NR1><RMT>
Query example: none
STATus:QUEStionable:ENABle
Description: This command sets or reads the value of the Questionable Enable
register. The register is a mask which enables specific bits from the
Questionable Event register to set the questionable summary
(QUES) bit of the Status Byte register.
Setting syntax: STATus:QUEStionable:ENABle<space><NR1><PMT>
Setting parameters: <NR1>, 0 ~ 65535
Setting example: none
Query syntax:
STATus:QUEStionable:ENABle?[<space><MAX | MIN>]<PMT>
Return parameters: <NR1>, 0 ~ 65535
Header on: :STATUS:QUESTIONABLE:ENABLE<space><NR1><RMT>
Header off: <NR1><RMT>
Query example: none
STATus:QUEStionable:NTRansition
Description: This command makes the values of the Questionable NTR register
set or read.
These registers serve as polarity filters between the Questionable Enable and
Questionable Event registers, and result in the following actions:
* When a bit of the Questionable NTR register is set at 1, a 1-to-0 transition of
the corresponding bit in the Questionable Condition register will cause that
bit in the Questionable Event register to be set.
* When a bit of the Questionable PTR register is set at 1, a 0-to-1 transition of
the corresponding bit in the Questionable Condition register will cause that
bit in the Questionable Event register to be set.
* If the two same bits in both NTR and PTR registers are set at 0, no
transition of that bit in the Questionable Condition register can set the