Cameron NUFLO 1141C, Руководство пользователя

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Appendix C: Principles of Operation
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Appendix C: Principles of Operation:
The Scanner 1141 was based on the following principles of operation.
Central Processing Unit (CPU)
The system board utilizes a microcomputer, which provides an interrupt controller, a clock generator,
and a demultiplexed data and address bus. In addition, it contains two serial ports, an 8-bit
comparator port, and digital control lines that can be used for interfacing with various types of digital
I/O. Clock control, as well as halt and stop methods, allow the CPU to minimize system power.
Memory
There are three types of memory in the Scanner 1141: program FLASH memory, random access
memory (RAM), and non-volatile random access memory (NVRAM).
Programs are stored in FLASH memory. FLASH memory enables the user to load new firmware
from an IBM-compatible PC into the Scanner 1141 using WinsLoad or ScanFLASH.
RAM is used as a temporary storage during normal program execution. RAM is volatile; any data
held in RAM is lost if a power failure occurs.
NVRAM is the system’s long-term storage memory for large blocks of vital data (e.g. configuration
data, logs, etc.) that must be protected if there is a power failure. NVRAM power is backed by a
small replaceable on-board lithium battery. If a loss of voltage is detected, the system immediately
saves all necessary data in the NVRAM. When power is restored, the computer resumes exactly
where it stopped when the power failed. The NVRAM is guarded against changes. NVRAM is only
written when there is a configuration change, a power failure, or if a system restart is performed.
This restriction protects vital configuration and measurement data from being lost if there is an
electrical transient or an uncontrolled program.
FPGA
A Field Programmable Gate Array (FPGA) is used to provide support logic for the CPU as well as
provide a number of additional I/O ports. This RAM-based program is loaded from FLASH memory
at system startup, allowing the logic to be modified and updated along with the application code,
adding flexibility to the system.
The FPGA generates the entire read and write information for the memory, I/O spaces, as well as
chip select outputs for all the memory devices.
In addition, the FPGA contains logic for:
•
controlling interrupts
•
a programmable counter for generating the system “heartbeat interrupt”