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[Table of Camera Link bit assignment] (Showing correspondence relation between before and after encoding)
Camera Link port
Camera
signal name
I/O
Remark
Strobe
CLK
O
Pixel clock
LVAL
LDV
O
Horizontal synchronous timing
FVAL
FDV
O
Vertical synchronous timing
DVAL
-
O
(Fixed to H level)
Spare
-
O
(Fixed to H level)
CC1
Vinit2
I
Asynchronous shutter trigger
CC2
(reserved)
I
(Reserved for future products)
CC3
(reserved)
I
(Reserved for future products)
CC4
(reserved)
I
(Reserved for future products)
SerTFG
TXD
O
URAT transmission data (Same timing as conventional RS-232C)
SerTC
RXD
I
URAT reception data (Same timing as conventional RS-232C)
[Table of Camera Link data assignment]
8 bit
TAP1
TAP2 TAP3 TAP4
Camera
signal name
A0
B0
C0
D0
D00
0
Lowermost data
A1
B1
C1
D1
D01
0
A2
B2
C2
D2
D02
0
A3
B3
C3
D3
D03
0
A4
B4
C4
D4
D04
0
A5
B5
C5
D5
D05
0
A6
B6
C6
D6
D06
0
A7
B7
C7
D7
D07
0
Uppermost data at the time of 8-bit scale capturing
Unused output
-
(Fixed to L level)
10bit
TAP1
TAP2 TAP3 TAP4
Camera
signal name
A0
C0
E0
D0
D00
0
Lowermost data
A1
C1
E1
D1
D01
0
A2
C2
E2
D2
D02
0
A3
C3
E3
D3
D03
0
A4
C4
E4
D4
D04
0
A5
C5
E5
D5
D05
0
A6
C6
E6
D6
D06
0
A7
C7
E7
D7
D07
0
B0
B4
F0
F4
D08
0
B1
B5
F1
F5
D09
0
Uppermost data at the time of 10-bit scale capturing
Unused output
-
0
(Fixed to L level)
* The port assignment is in conformity to
“
Medium/Base Configuration
”,
the standard of Camera Link.
Fixing screw × 2
Twin-Ax cable
MDR-26 Twin-Ax cable harness (male)
MDR-26 Twin-Ax cable harness (male)
Fixing screw × 2
Fig.3-2 External view of Camera Link cable assembly