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8. Timing Chart
● Pixel clock timing (common in various operation modes)
(Note) The above timing represents the signal timing before being encoded to serial data by the channeling device on the side of
the sending end (the part circled in the above right figure). If signal conversion from serial to parallel is made by a channel
link device in accordance with the standard of Camera Link on the side of the receiving end, the phase relationship
between the clock and the data after decoding will be different from that of the above timing due to the structural nature of
a channel link device. (In the case of the output from a channel link device, the data are aligned with the falling of the clock
signal.) As a general rule, this variation in timing is correctly adjusted at the capture timing of a capture board, the equal
definition file to that of the conventional parallel output type can be used for capturing.
(Note) When a channel link device is mounted directly to the capture interface on the user side, instead of using a commercially
available capture board that supports Camera Link, it is necessary to pay close attention to the descriptions of the data
sheet of the channel link device including the phase relationship between data and clock prior to the use.
(!) 10 or 8 bit x 4 tap output is adopted for FC2600CL.
(!) In the case of FC2600CL, the image signals are output in order from the upper left even in QUAD output mode (60fps) as
they are sorted using internal buffer.
[Phase relationship between clock output and data]
１ＣＬＫ＝２５．０ｎＳ
１０ｎｓ(max)
Cl o ck ou tp u t
Di g it a l da t a
Ｔ ａ ｐ １ ～ ４
１ ０ o r ８ b it ea ch
CL K
Ａ／Ｄ 10bit
Camera Link
connector
C
h
an
n
el
L
in
k
( LDV, F DV)
C
a
m
e
ra
L
in
k
B
a
s
e
C
o
n
fi
g
r
at
io
n
DEMULTIPLEX.
10/8bit
10/8bit
Tap1
P CLK
1／1
CLK
Ａ／Ｄ 10bit
Ａ／Ｄ
10bit
Ａ／Ｄ
10bit
Tap2
Tap3
Tap4
10/8bit
10/8bit
