CAES RISC-V NOEL-ARTYA7-EX, Руководство пользователя, Страница: 6 / 12

NOEL-ARTYA7-EX-UM
Jul 2022, Version 2.0 6
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NOEL-ARTYA7-EX
3 Architecture
3.1 Cores
The architecture is based on cores from the GRLIB IP library. The vendor and device identifiers for
each core can be extracted from the plug & play information. The used IP cores are listed in table 3.
3.2 Interrupts
The NOEL-ARTYA7-EX example designs use the same interrupt assignment for all configurations.
See the description of the individual cores for how and when the interrupts are raised. All interrupts
are handled by the interrupt controller and forwarded to the processor.
3.3 Memory map
The example designs use the same memory map for all standard configurations. The memory map
shown in table 5 is based on the AMBA AHB address space. An access to addresses outside the
Table 3.
Used IP cores
Core Function Vendor Device
AHBCTRL AHB Arbiter & Decoder 0x01 -
APBCTRL AHB/APB Bridge 0x01 0x006
NOEL-V NOEL-V RISC-V 64-bit processor 0x01 0xBD
RVDM RISC-V Debug Module 0x01 0xBE
AHBUART Serial/AHB debug interface 0x01 0x007
AHBJTAG JTAG/AHB debug interface 0x01 0x01C
AHBSTAT AHB failing address register 0x01 0x052
APBUART 8-bit UART 0x01 0x00C
GPTIMER Modular timer unit with watchdog 0x01 0x011
GRETH 10/100 Mbit Ethernet MAC 0x01 0x01D
GRGPIO General purpose I/O port 0x01 0x01A
L2CACHE Level-2 Cache Controller 0x01 0x04B
Xilinx MIG Xilinx DDR3 MIG - with GRLIB wrapper 0x01 0x090
Table 4. Interrupt assignment
Core Interrupt Comment
AHBSTAT 4
APBUART 1
GPTIMER 2, 3
GRETH_GBIT 5