NOEL-ARTYA7-EX-UM
Jul 2022, Version 2.0
4
Cobham Gaisler AB
Kungsgatan | SE-411 19 | Goteborg | Sweden
+46 31 7758650 | www.caes.com/gaisler
NOEL-ARTYA7-EX
2
Example designs
2.1
Overview
The NOEL-ARTYA7-EX example designs are based on a common architecture. The architecture is
centered around the AMBA [AMBA] Advanced High-speed Bus (AHB), to which the processor(s)
and other high-bandwidth units are connected. Low-bandwidth units are connected to the AMBA
Advanced Peripheral Bus (APB) which is accessed through an AHB to APB bridge. The architecture
for the basic design is shown in figure 1. Please also note that while not shown in the block diagram
above, the Ethernet controller (GRETH) is also connected to the main AHB bus and not only the
Debug AHB bus.
The full NOEL-ARTYA7 architecture includes the following modules:
•
NOEL-V with 16 KiB instruction cache and 16 KiB data cache.
•
Debug Support Unit with UART, Ethernet, and JTAG Debug Links
•
Level-2 cache controller
•
Xilinx MIG DDR3 SDRAM controller
•
Timer unit with two 32-bit timers
•
Platform-Level Interrupt Controller
•
UART with FIFO and separate baud rate generator
•
General purpose I/O port (GPIO).
•
AMBA AHB status register
The GRLIB IP library contains a template design that has been used as the base for NOEL-ARTYA7-
EX designs. The template design can easily be extended to add additional GRLIB IP library IP cores
such as:
•
Memory controllers with EDAC
•
SpaceWire links with CRC support and hardware RMAP target
•
SpaceFibre links
•
Mil-Std-1553 BC/BM/RT
A full list of GRLIB IP library components can be found in [GRIP]. The GRLIB user’s manual is
available on-line [GRLIB].
Figure 1.
Architectural block diagram of NOEL-ARTYA7-EX