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NOEL-ARTYA7-EX-UM

Jul 2022, Version 2.0

5

NOEL-ARTYA7-EX

 

Cobham Gaisler AB

Kungsgatan | SE-411 19 | Goteborg | Sweden

+46 31 7758650 | www.caes.com/gaisler

2.2

Configurations

Table 2 below lists the NOEL-ARTYA7-EX example configurations. The bitstreams with example

designs are intended to cover a wide range of application scenarios.   Note that current available bit

-

streams have some limitations compared to the listed configuration. 
The bitstreams are available for download from https://gaisler.com/NOEL-ARTYA7

Note:

 The configurations above are examples on how to use the GRLIB IP cores on ARTYA7. All IP

cores have several configuration parameters and are individually configurable.

Note:

 The NOEL-V processor can be configured in several different standard configurations, includ

-

ing more RV32 variants, the configurations are listed at https://www.gaisler.com/NOEL-V

Note:

 While  software  may  report  that  fault-tolerance  is  enabled  for  the  example  designs,  the  bit

-

streams are not suitable for use in harsh environments.

Table 2.

Example configurations

Configuration name

MC32L-SC

GP32L-SC

MC64-SC

GP64L-SC

Artix-7 device

XC7A100T

XC7A100T

XC7A100T

XC7A100T

Processor

NOEL-V

NOEL-V

NOEL-V

NOEL-V

RISC-V extensions*

RV64-IMA

RV32-

IMACFD

RV64-

IMCAFD

RV64-

IMCAFD

Memory Management Unit 

(MMU)

No

Yes

No

Yes

Number of processor cores 1

1

1

1

Level-1 cache

8+8 KiB

16+16 KiB

8+8 KiB

16+16 KiB

Hardware multiply&divide Yes

Yes

Yes

Yes

Floating Point Unit

No

nanoFPU

nanoFPU

nanoFPU

Physical Memory Protec

-

tion (PMP)

Yes

Yes

Yes

Yes

Level-2 cache

Yes

Yes

Yes

Yes

UART Debug Link

Yes

Yes

Yes

Yes

JTAG Debug Link

Yes

Yes

Yes

Yes

Ethernet MAC 10/100 Mbit Yes

Yes

Yes

Yes

Memory Controller

Xilinx DDR3 

MIG & 

AHBROM

Xilinx DDR3 

MIG & 

AHBROM

Xilinx DDR4 

MIG & 

AHBROM

Xilinx DDR4 

MIG & 

AHBROM

Standard peripherals

Yes

Yes

Yes

Yes

*Parts of the Bit manipulation and Encryption RISC-V extensions are also 

included. See NOEL-V section in  GRLIB IP Core User's Manual for more 

details

Содержание RISC-V NOEL-ARTYA7-EX

Страница 1: ...ler RISC V standard PMP RISC V standard debug support Level 2 cache DDR4 SDRAM UART Timers GPIO port Status registers Ethernet 10 100 Mbit MAC interface Description The NOEL ARTYA7 FPGA bitstreams are...

Страница 2: ...2 Document revision history 3 1 3 Reference documents 3 2 Example designs 4 2 1 Overview 4 2 2 Configurations 5 3 Architecture 6 3 1 Cores 6 3 2 Interrupts 6 3 3 Memory map 6 3 4 IP core documentation...

Страница 3: ...n Hi Rel and Synopsys Synplify Premier This document describes ready made FPGA configurations bitstreams that have been built from a GRLIB template design More information about the NOEL V processor i...

Страница 4: ...Debug AHB bus The full NOEL ARTYA7 architecture includes the following modules NOEL V with 16 KiB instruction cache and 16 KiB data cache Debug Support Unit with UART Ethernet and JTAG Debug Links Le...

Страница 5: ...ftware may report that fault tolerance is enabled for the example designs the bit streams are not suitable for use in harsh environments Table 2 Example configurations Configuration name MC32L SC GP32...

Страница 6: ...designs use the same memory map for all standard configurations The memory map shown in table 5 is based on the AMBA AHB address space An access to addresses outside the Table 3 Used IP cores Core Fu...

Страница 7: ...FFFFFFF DDR4 SDRAM area AHBROM 0xC0000000 0xC001FFFF Registers CLINT 0xE0000000 0xE000FFFF Registers PLIC 0xF8000000 0xFBFFFFFF Registers GPTIMER 0xFC000000 0xFC0000FF Registers APBUART0 0xFC001000 0x...

Страница 8: ...isler NOEL ARTYA7 EX 3 4 IP core documentation This user manual does not contain IP core documentation Please refer to the GRLIB IP Core User s Manual GRIP available at http gaisler com products grlib...

Страница 9: ...teborg Sweden 46 31 7758650 www caes com gaisler 3 5 Signals Please see the NOEL ARTYA7 EX Quick Start Guide QSG for information on FPGA pinout 3 6 Resource utilization Resource utilization is describ...

Страница 10: ...EX designs Toolchains and run time environments are available for download via http gaisler com 4 2 Programming the FPGA device and connecting with GRMON3 Please see the NOEL ARTYA7 EX Quick Start Gui...

Страница 11: ...2022 Version 2 0 11 Cobham Gaisler AB Kungsgatan SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler NOEL ARTYA7 EX 5 Ordering information Please contact sales gaisler com for information on...

Страница 12: ...the application or use of any product or service described herein except as expressly agreed to in writing by Cobham nor does the purchase lease or use of a product or service from Cobham convey a lic...

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