PRELIMINARY
Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V1729 4 Channel 12 Bit Sampling ADC
22/06/2005
3
NPO:
Filename:
Number of pages:
Page:
00109/04:V1729.MUTx/03 V1729_REV3.DOC
38
32
The sub-addresses are organized by type. For more detail on their specific use in VME
or GPIB, refer to 4.6.
The functions of these different commands and registers are described below :
RESET BOARD : reset of the board. Restores idle state. Does not modify the value
loaded in the different registers.
LOAD TRIGGER THRESHOLD DAC : permits transfer of the pre-loaded value in the
register of the DAC towards the analog converter itself.
START ACQUISITION : launches the data acquisition and resets the INTERRUPT
register. When this is finished, the INTERRUPT signal will be validated and transmitted
towards the bus interfaces. This latter signal will also be able to be read at the sub-
address h80.
SOFTWARE TRIGGER : permits generation of a trigger coming from a bus interface.
TRIGGER THRESHOLD DAC : register of pre-loading of the DAC. This 12-bit register
covers the range from –0.5V (000) to +0.5V (FFF). By GPIB, one has access to the
MSBs and LSBs via 2 distinct sub-addresses. The access is necessarily made in the
order MSB (0B) then LSB (0A). By VME, the access is made via a single sub-address
(0A). After loading of this register, one must transfer the value in the analog converter via
the LOAD_TRIGGER THRESHOLD DAC (09) command.
RAM DATA : this is the memory where the data is stored. As above, the access to the
data is made differently in GPIB and in VME (see NB OF BYTES TO READ IN BLOCK
MODE). The addressing is indirect, the internal address of the RAM being defined by the
RAM_INT_ADD counter located in the ALTERA.
RAM_INT_ADD : this 16-bit counter fixes the internal address of the RAM for the bus
access in progress. It is set back to zero by the RESET_BOARD command and by the
interruption at the end of the acquisition phase. For a direct access to an address or a
given group of addresses, one must pre-load it.
MAT CTRL REGISTER : this is a control register for the acquisition parameters. It covers
9 bits. The bits followed by an asterisk are reserved and must be left at zero.
Bits Name Default
Function
0
BWL
0
Regulates the bandwidth of the input amplifiers with BWL1 (see 4.5.4 )
1
BWL1
0
Regulates the bandwidth of the input amplifiers with BWL (see 4.5.4 )
2
EBP
0
At 1, authorizes the bypass of the input signal towards the ADC
3
ELD* -
Reserved
4
ENVDLL* 0
Reserved
5
EIR* 0
Reserved
6
EPR
0
At 1, forces the permanent supply of the reading amplifiers
7
EPW
0
At 1, forces the permanent supply of the writing amplifiers
8
ESO
0
At 1, authorizes the SYNC_OUT signal to be output from the board (thanks to
the corresponding strap S4)
PRETRIG : this 16-bit register fixes the delay in periods of Fp between the START
ACQUISITION and the internal authorization to validate a trigger, whatever the source of
the latter. For proper functioning, it must be fixed at a minimum of 5000 for an Fp
frequency of 50MHz and at 10000 for a frequency of 100MHz. By default, its value is
10240.
POSTTRIG : this 16-bit register fixes the delay in periods of Fp between the trigger and
the stopping of the acquisition. It permits in practice choosing the useful position of the
signal in the window of 2560 cells. By default, its value is 64.
TRIGGER TYPE : this 5-bit register fixes the source and the useful edge of the trigger.
