Brocade Communications Systems Fabric OS v7.1.0, Руководство по устранению неисправностей

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36 Fabric OS Troubleshooting and Diagnostics Guide
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Segmented fabrics
3
Testing a port’s external transmit and receive path
1. Connect to the switch and log in as admin.
2. Connect the port you want to test to any other switch port with the cable you want to test.
3. Enter the portLoopbackTest -lb_mode 2 command.
Testing a switch’s internal components
1. Connect to the switch and log in as admin.
2. Connect the port you want to test to any other switch port with the cable you want to test.
3. Enter the portLoopbackTest -lb_mode 5 command where 5 is the operand that causes the test
to run on the internal switch components (this is a partial list—refer to the Fabric OS Command
Reference for additional command information):
[-nframes count ]—Specify the number of frames to send.
[-lb_mode mode ]—Select the loopback point for the test.
[-spd_mode mode ]—Select the speed mode for the test.
[-ports itemlist ]—Specify a list of user ports to test.
Testing components to and from the HBA
1. Connect to the switch and log in as admin.
2. Enter the portTest command (refer to the Fabric OS Command Reference for information on
the command options).
See Table 7 on page 36 for a list of additional tests that can be used to determine the switch
components that are not functioning properly. Refer to the Fabric OS Command Reference for
additional command information.
The HBA's bcu fcDiag
--
linkbeacon command can be used to beacon a target port on the switch.
For more information on using this command, refer to the Brocade Adapters Administrator’s Guide .
Segmented fabrics
Fabric segmentation is generally caused by one of the following conditions:
•
Incompatible fabric parameters (see “Reconciling fabric parameters individually” on page 37).
TABLE 7
Switch component tests
Test Function
portBeacon Sets port beaconing mode.
portLoopbackTest Performs a functional test of port N to N path. Verifies the functional components of the
switch.
turboRamTest Verifies that the on chip SRAM located in the 4 and 8 Gbps ASIC is using the Turbo-Ram BIST
circuitry. This allows the BIST controller to perform the SRAM write and read operations at a
much faster rate.