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System Control & I/O Port Table (IC801)
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Control Port Functions
1
PA23/WRHH
USB RESET
USB Reset Signal
Active L
O
2
PE14/TIOC4C/DACK0/AH
IC RESET
Power on/off control except FAN and LAMP
Active L
O
3
PA22/WRHL
CLB_CPU
SAM3
O
4
PA21/CASHH
NET_SP_RESET
PJ Net Reset
L : Reset
O
5
PE15/TIOC4D/DACK1/IRQOUT
POWER SW
LAMP LED
L: Power OFF H: Power ON
O
6
VSS
GND
7
PC0/A0
ADDRESS0
Address Bus 0
O
8
PC1/A1
ADDRESS1
Address Bus 1
O
9
PC2/A2
ADDRESS2
Address Bus 2
O
10
PC3/A3
ADDRESS3
Address Bus 3
O
11
PC4/A4
ADDRESS4
Address Bus 4
O
12
VCC
5V
13
PC5/A5
ADDRESS5
Address Bus 5
O
14
VSS
GND
15
PC6/A6
ADDRESS6
Address Bus 6
O
16
PC7/A7
ADDRESS7
Address Bus 7
O
17
PC8/A8
ADDRESS8
Address Bus 8
O
18
PC9/A9
ADDRESS9
Address Bus 9
O
19
PC10/A10
ADDRESS10
Address Bus 10
O
20
PC11/A11
ADDRESS11
Address Bus 11
O
21
PC12/A12
ADDRESS12
Address Bus 12
O
22
PC13/A13
ADDRESS13
Address Bus 13
O
23
PC14/A14
ADDRESS14
Address Bus 14
O
24
PC15/A15
ADDRESS15
Address Bus 15
O
25
PB0/A16
ADDRESS16
Address Bus 16
O
26
VCC
5V
27
PB1/A17
ADDRESS17
Address Bus 17
O
28
VSS
GND
29
PA20/CASHL
SCL 1
IIC Bus 1 Clock
I/O
30
PA19/BACK/DRAK1
SDA 1
IIC Bus 1 Data
I/O
31
PB2/IRQ0/POE0/RAS
RESET_CPU
IP Reset
O
32
PB3/IRQ1/POE1/CASL
Not used
33
PA18/BREQ/DRAK0
SYS SW
Peripheral IC Power SW (ON=L, OFF=H)
O
34
PB4/IRQ2/POE2/CASH
AFT-V
Vertical Sync. Signal for Panel Drive
I
35
VSS
GND
36
PB5/IRQ3/POE3/RDWR
SDA 6
IIC Bus 6 Data
I/O
37
PB6/IRQ4/A18/BACK
ADDRESS18
Address Bus 18
O
38
PB7/IRQ5/A19/BREQ
ADDRESS19
Address Bus 19
O
39
PB8/IRQ6/A20/WAIT
ADDRESS20
Address Bus 20
O
40
VCC
5V
41
PB9/IRQ7/A21/ADTRG
ADDRESS21
Address Bus 21
O
42
VSS
GND
43
PA14/RD
READ
Read signal
Active L
O
44
WDTOVF
WDT
Over flow output from Watch dog timer
Not used
O
45
PD31/D31/ADTRG
RTS
RS232C RTS (Request To Send)
Not used
I
46
PD30/D30/IRQOUT
PFC_SW
Main Power ON/OFF
Fan ON = H
O
47
PA13/WRH
WRH
Write signal (Higher 8 bit)
Active L
O
48
PA12/WRL
WRL
Write signal (Lower 8 bit)
Active L
O
49
PA11/CS1
SRAM_CS
SRAM Chip Select
Active L
O
50
PA10/CS0
CS0
Flash Memory Chip Select
Active L
O
51
PA9/TCLKD/IRQ3
SCL 2
IIC Bus 2 Clock
I/O
52
PA8/TCLKC/IRQ2
SDA 2
IIC Bus 2 Data
I/O
53
PA7/TCLKB/CS3
CS3
USB / IP / CHO / iO EXP Chip Select
Active L
O
54
PA6/TCLKA/CS2
CS2
SAM3 Chip Select
Active L
O
55
VSS
GND
56
PD29/D29/CS3
IPOUT_CPU
IP Output Enable
AV = L
O
57
PD28/D28/CS2
PW_SEL
PW365 RS232C Select
SAM3 = L
O
58
PD27/D27/DACK1
SCL 6
IIC Bus 6 Clock
O
59
PD26/D26/DACK0
SCL 5
IIC Bus 6 Data
O
60
PD25/D25/DREQ1
PW_OUT0
PW_365 Data output
(reserve)
O
61
VSS
GND
62
PD24/D24/DREQ0
NET_H/L
PJ Net Command waiting
Active L
O
63
VCC
5V
64
PD23/D23/IRQ7
SAM3_INT
SAM3
(reserve)
I
65
PD22/D22/IRQ6
DVI_OUT
DVI = L
O
66
PD21/D21/IRQ5
CHO_RESET
M66230 (for LAMP Control) Reset H - L - H = Reset
O
67
PD20/D20/IRQ4
SAM_HZ
SAM3 High impedance
Hi-Z = L
O
68
PD19/D19/IRQ3
CHO_INT
M66230 (for LAMP Control) Dividing signal input
Active L
I
69
PD18/D18/IRQ2
SDA 5
IIC Bus 5 Data
I/O
70
PD17/D17/IRQ1
PW_IN0
PW365 AD Power down input
Down = L
I
71
VSS
GND
Pin No.
Name
Function Name
Function
Polarity
I/O
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