BL602/604 Reference Manual
When the interrupt is generated, the interrupt status can be queried by the gpadc_pos_satur, and gpadc_neg_satur
registers, and the interrupt can be cleared by gpadc_pos_satur_clr and gpadc_neg_satur_clr. This function can be
used to determine whether the input voltage is abnormal.
4.3.7 ADC FIFO
The ADC module has a FIFO with a depth of 32 and a data width of 26bits. After the ADC completes the conversion,
it will automatically push the result into the FIFO. The ADC’s FIFO has the following status and interrupt management
functions:
• FIFO full status
• FIFO is not empty
• FIFO Overrun interrupt
• FIFO Underrun interrupt
When an interrupt occurs, the interrupt flag can be cleared by the corresponding clear bit.
Using the ADC’s FIFO, users can implement three modes of data acquisition: query mode, interrupt mode, and DMA
mode.
Query mode
The CPU polls the gpadc_rdy bit. When this control bit is set, it indicates that there is valid data in the FIFO. The CPU
can obtain the number of FIFO data according to gpadc_fifo_data_count and read these data from the FIFO.
Interrupt mode
The CPU sets gpadc_rdy_mask to 0, and the ADC will generate an interrupt when there is data in the FIFO. The user
can use the interrupt function to obtain the number of FIFO data according to gpadc_fifo_data_count and read these
data from the FIFO. Then set gpadc_rdy_clr to clear the interrupt.
DMA mode
The user sets the gpadc_dma_en control bit, which can cooperate with DMA to complete the transfer of data to
memory. When using the DMA mode, the gpadc_fifo_thl is used to set the threshold of the number of data sent by
the ADC FIFO by the FIFO. When the DMA receives the request, it will automatically transfer the specified number of
results from the FIFO to the corresponding memory according to the parameters set by the user.
4.3.8 ADC configuration process
Setting the ADC clock
According to the ADC conversion speed requirements, determine the working clock of the ADC, set the ADC clock
source and frequency division of the GLB module, and combine with gpadc_clk_div_ratio to determine the final working
module’s clock frequency.
BL602/604 Reference Manual
51/ 195
@2020 Bouffalo Lab
