Bose FREESPACE 4400, Руководство по обслуживанию

Страница: 104 / 107

104
Block Diagram
16-bit Memory Code
16-bit Memory Address
16-b
it I
n
stru
cti
o
n
Bu
s
24-
b
it
P
rog
ram
Coun
te
r Bus
8-b
it
Data Bu
s
24-b
it
Data Ad
d
ress Bu
s
8
-b
it I
n
tern
a
l Bu
s
P
e
ri
p
h
eral
I
n
terface Uni
t
VDD VSS VSS1
P3(A16) P1(A17) P2(A15-8) P0(AD7-0)
RST
XTAL2
XTAL1
NMI
EA#/VPP
ALE/PROG#
PSEN#
Timers 0, 1 and 2
Event and Waveform
Controller
TWI/SPI/ m Wire
Controller
Watchdog Timer
Power Management
Clock Unit
Clock System Prescaler
Keyboard Interface
Bus Interface Unit
CPU
PORTS 0-3
Interrupt Handler
Unit
RAM
1 Kbyte
ROM
UART
Baud Rate Generator
AWAIT#
EPROM
OTPROM
32 KB
VSS2
TSC80251G2D 44-pin PLCC Package
TSC80251G2D
P1.
4
/C
EX1/
SS#
P1.
3
/C
EX0
P1.
2
/E
C
I
P1.
1
/T
2EX
P1.
0
/T
2
VSS1 VD
D
P0.
0
/A
D
0
P0.
1
/A
D
1
P0.
2
/A
D
2
P0.
3
/A
D
3
P
3
.7/A
16/RD#
XT
AL
2
XT
AL
1
VSS
VSS
2
P2.
0/A
8
P2.
1/A
9
P2.
2
/A
10
P2.
3/A
1
1
P2.
4
/A
12
P3
.6
/WR
#
39
38
37
36
35
34
33
32
29
30
31
7
8
9
10
11
12
13
14
17
16
15
18 19 20 21 22 23 24 25 26 27 28
6 5 4 3 2
44 43 42 41 40
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
PSEN#
ALE/PROG#
NMI
P2.7/A15
P2.6/A14
P2.5/A13
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
RST
P3.0/RXD
AWAIT#
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
1
TSC80251G2D Pin Assignment
e m a N
C C L P
e m a N C C L P
2 S S V
3 2 1 S S V
1
8 A / 0 . 2 P 4 2 2 T / 0 . 1 P 2
9 A / 1 . 2 P
5 2 X E 2 T / 1 . 1 P
3
0 1 A / 2 . 2 P
6 2 I C E / 2 . 1 P
4
1 1 A / 3 . 2 P 7 2 0 X E C / 3 . 1 P 5
2 1 A / 4 . 2 P
8 2 # S S / 1 X E C / 4 . 1 P
6
3 1 A / 5 . 2 P 9 2 O S I M / 2 X E C / 5 . 1 P 7
8 P1.6/CEX3/SCL/SCK/WAIT 30 P2.6/A14
9 P1.7/A17/CEX4/SDA/MOSI/WCL 31 P2.7/A15
# N E S P 2 3 T S R 0 1
# G O R P / E L A 3 3 D X R / 0 . 3 P 1 1
I M N
4 3
# T I A W A 2 1
P P V / # A E 5 3 D X T / 1 . 3 P 3 1
7 D A / 7 . 0 P
6 3
# 0 T N I / 2 . 3 P 4 1
6 D A / 6 . 0 P
7 3
# 1 T N I / 3 . 3 P 5 1
5 D A / 5 . 0 P 8 3 0 T / 4 . 3 P 6 1
4 D A / 4 . 0 P
9 3
1 T / 5 . 3 P 7 1
3 D A / 3 . 0 P
0 4
# R W / 6 . 3 P 8 1
2 D A / 2 . 0 P 1 4 # D R / 6 1 A / 7 . 3 P 9 1
1 D A / 1 . 0 P
2 4
2 L A T X 0 2
0 D A / 0 . 0 P 3 4 1 L A T X 1 2
D D V 4 4 S S V 2 2
Product Name Signal Description
Signal
Name Type Description
A17 O
18
th
Address Bit
Output to memory as 18th external address bit (A17) in extended bus
applications, depending on the values of bits RD0 and RD1 in UCONFIG0
byte.
A16 O
17
th
Address Bit
Output to memory as 17th external address bit (A16) in extended bus
applications, depending on the values of bits RD0 and RD1 in UCONFIG0
byte.
A15:8
(1)
O
Address Lines
Upper address lines for the external bus.
AD7:0
(1)
I/O
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
ALE O
Address Latch Enable
ALE signals the start of an external bus cycle and indicates that valid
address information are available on lines A16/A17 and A7:0. An external
latch can use ALE to demultiplex the address from address/data bus.
AWAIT# I
Real-time Asynchronous Wait States Input
When this pin is active (low level), the memory cycle is stretched until it
becomes high. When using the Product Name as a pin-for-pin replacement
for a 8xC51 product, AWAIT# can be unconnected without loss of
compatibility or power consumption increase (on-chip pull-up).
Not available on DIP package.
CEX4:0 I/O
PCA Input/Output pins
CEXx are input signals for the PCA capture mode and output signals for
the PCA compare and PWM modes.
EA# I
External Access Enable
EA# directs program memory accesses to on-chip or off-chip code memory.
For EA# = 0, all program memory accesses are off-chip.
For EA# = 1, an access is on-chip ROM if the address is within the range of
the on-chip ROM; otherwise the access is off-chip. The value of EA# is
latched at reset.
For devices without ROM on-chip, EA# must be strapped to ground.
ECI O
PCA External Clock input
ECI is the external clock input to the 16-bit PCA timer.
MISO I/O
SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave
peripheral. When SPI is in slave mode, MISO outputs data to the master
controller.
MOSI I/O
SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data to the slave peripheral.
When SPI is in slave mode, MOSI receives data from the master controller.
INT1:0# I
External Interrupts 0 and 1
INT1#/INT0# inputs set IE1:0 in the TCON register. If bits IT1:0 in the
TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#.
If bits IT1:0 are cleared, bits IE1:0 are set by a low level on INT1#/INT0#.
Integrated Circuit Diagrams
TSC80251G2D, Microprocessor