Bose FREESPACE 4400, Руководство по обслуживанию

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105
NMI I
Non Maskable Interrupt
Holding this pin high for 24 oscillator periods triggers an interrupt.
When using the Product Name as a pin-for-pin replacement for a 8xC51
product, NMI can be unconnected without loss of compatibility or power
consumption increase (on-chip pull-down).
Not available on DIP package.
P0.0:7 I/O
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. To avoid
any paraitic current consumption, Floating P0 inputs must be polarized to
V
DD
or V
SS
.
P1.0:7 I/O
Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups. P1 provides
interrupt capability for a keyboard interface.
P2.0:7 I/O
Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
P3.0:7 I/O
Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
PROG# I
Programming Pulse input
The programming pulse is applied to this input for programming the on-chip
EPROM/OTPROM.
PSEN# O
Program Store Enable/Read signal output
PSEN# is asserted for a memory address range that depends on bits RD0
and RD1 in UCONFIG0 byte.
RD# O
Read or 17
th
Address Bit (A16)
Read signal output to external data memory depending on the values of
bits RD0 and RD1 in UCONFIG0 byte.
RST I
Reset input to the chip
Holding this pin high for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage greater than V
IH1
is applied, whether or not the oscillator is running.
This pin has an internal pull-down resistor which allows the device to be
reset by connecting a capacitor between this pin and VDD.
Asserting RST when the chip is in Idle mode or Power-Down mode returns
the chip to normal operation.
RXD I/O
Receive Serial Data
RXD sends and receives data in serial I/O mode 0 and receives data in
serial I/O modes 1, 2 and 3.
SCL I/O
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to
slave peripherals. When TWI controller is in slave mode, SCL receives
clock from the master controller.
SCK I/O
SPI Serial Clock
When SPI is in master mode, SCK outputs clock to the slave peripheral.
When SPI is in slave mode, SCK receives clock from the master controller.
SDA I/O
TWI Serial Data
SDA is the bidirectional TWI data line.
SS# I
SPI Slave Select Input
When in Slave mode, SS# enables the slave mode.
Product Name Signal Description (Continued)
Signal
Name Type Description
T1:0 I/O
Timer 1:0 External Clock Inputs
When timer 1:0 operates as a counter, a falling edge on the T1:0 pin
increments the count.
T2 I/O
Timer 2 Clock Input/Output
For the timer 2 capture mode, T2 is the external clock input. For the Timer 2
clock-out mode, T2 is the clock output.
T2EX I
Timer 2 External Input
In timer 2 capture mode, a falling edge initiates a capture of the timer 2
registers. In auto-reload mode, a falling edge causes the timer 2 register to
be reloaded. In the up-down counter mode, this signal determines the
count direction: 1 = up, 0 = down.
TXD O
Transmit Serial Data
TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial
I/O modes 1, 2 and 3.
VDD PWR
Digital Supply Voltage
Connect this pin to +5V or +3V supply voltage.
VPP I
Programming Supply Voltage
The programming supply voltage is applied to this input for programming
the on-chip EPROM/OTPROM.
VSS GND
Circuit Ground
Connect this pin to ground.
VSS1 GND
Secondary Ground 1
This ground is provided to reduce ground bounce and improve power
supply bypassing. Connection of this pin to ground is recommended.
However, when using the TSC80251G2D as a pin-for-pin replacement for a
8xC51 product, VSS1 can be unconnected without loss of compatibility.
Not available on DIP package.
VSS2 GND
Secondary Ground 2
This ground is provided to reduce ground bounce and improve power
supply bypassing. Connection of this pin to ground is recommended.
However, when using the TSC80251G2D as a pin-for-pin replacement for a
8xC51 product, VSS2 can be unconnected without loss of compatibility.
Not available on DIP package.
WAIT# I
Real-time Synchronous Wait States Input
The real-time WAIT# input is enabled by setting RTWE bit in WCON
(S:A7h). During bus cycles, the external memory system can signal
‘system ready’ to the microcontroller in real time by controlling the WAIT#
input signal.
WCLK O
Wait Clock Output
The real-time WCLK output is enabled by setting RTWCE bit in WCON
(S:A7h). When enabled, the WCLK output produces a square wave signal
with a period of one half the oscillator frequency.
WR# O
Write
Write signal output to external memory.
XTAL1 I
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this
pin. If an external oscillator is used, its output is connected to this pin.
XTAL1 is the clock source for internal timing.
Signal
Name Type Description
Notes:
The description of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the Non-Page mode chip con-
figuration. If the chip is configured in Page mode operation, port 0 carries the lower
address bits (A7:0) while port 2 carries the upper address bits (A15:8) and the data
(D7:0).
XTAL2 O
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this
pin. If an external oscillator is used, leave XTAL2 unconnected.
Integrated Circuit Diagrams
TSC80251G2D, Microprocessor