TELCOLINK DT - AccessDSL NTU
User Manual
Version: 2.5
Page 16 of 66
Service
DTE
Clock Mode
DCE
Clock Mode
DCE
Clock Direction
xDSL
Clock Mode
Nx64 only
Slave
internal
don’t care
Master
Slave
external
don’t care
Slave
Master
external
codirectional
Slave
Master don’t care
external
contradirectional
Master don’t care
Master
don’t care
don’t care
Master
Nx64 & fE1
Slave
from E1
don’t care
Master
Slave
from E1
don’t care
Slave
Master
don’t care
don’t care
don’t care
Note: Invalid clock modes are ruled out.
3.3.5 Nx64 Block Diagram
The following block diagram shows the receive and transmit path separately. Each direction
possesses a FIFO buffer and a PLL.
Figure 3-4: Nx64 Block Diagram
Rx
FIFO
Rx Framer
RxClk_xDSL
RxData_xDSL
Rx PLL
Osc.
FIFO Enable
RxClk_Nx64
RxData_Nx64
RxSync_xDSL
Tx
FIFO
Tx Framer
TxClk_xDSL
TxData_xDSL
Tx PLL
Osc.
FIFO Enable
TxClk_Nx64
TxData_Nx64
TxSync_xDSL
TxClk_E1
TxSync_E1
TxData_E1
Service
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