for more detail).
VERTICAL SENSITIVITY-The setting of the VER
TICAL SENSITIVITY control is determined primarily
by physical size of the transistor or semiconductor
being tested. Most small signal transistors, including
most small plastic case transistors, should be tested
at the 1 ma/Div position. Some small signal transis
tors, including several metallic case transistors,
should be tested at the 2 mA/Div position The 5 mA/
Div and 10 mA/Div positions are primarily for power
transistors. The 5 mA/Div is for low to medium
power transistors and include most plastic case
power transistors and those with self-contained heat
radiating cases. High power transistors should be
tested at 10 mA/Div. Power transistors may be tested
without their usual heat sinks if testing is limited to
a few seconds; just long enough to make the read
ing. It is especially important
to
keep testing time
short during periods of voltage breakdown and
current limiting to prevent overheating and thermal
runaway damage.
The curve tracer employs current limiting in the
collector voltage supply to prevent damage to the
transistor being tested. However, the point of current
limiting is increased with each step of the VERTICAL
SENSITIVITY control. Thus, the lowest acceptable
setting of the control must be used to protect small
transistors. Start with the lowest position (1 mA/Div)
and increase to a higher setting only as necessary.
STEP SELECTOR-The STEP SELECTOR switch
selects the base current steps. The approximate set
ting of this control also is somewhat related to the
physical size of the transistor. The fast set-up posi
tion (10 µ.A per step) is a good starting point for most
signal transistors. Very
High-gain
small signal tran
sistors will require a lower setting. Large signal and
power transistors will require a higher setting.
If transistor specification sheets are available, it
is desirable to use the manufacturer's data and set
the STEP SELECTOR to produce the specified col
lector current where Beta is to be measured. If data
sheets are not available, the general rule is
to
adjust
the STEP SELECTOR for the most curves displayed
on the VERTICAL SENSITIVITY range being used.
If the setting is too high, some of the curves may
reach the current limiting value and be superim
posed on each other, causing less than five curves
to be displayed. When more than one position dis
plays all five curves, select the position that pro
duces the most even spacing between curves.
The Volts per Step positions are for testing FET's.
In these positions, step polarity is reversed with
respect to the sweep voltage. The method of adjust
ment is the same; set for the maximum number of
curves and the most even spacing between curves
on the vertical range being used.
Sorting and Matching Transistors
A better method of oscilloscope set-up simplifies
sorting and matching of transistors when the types
are mixed or unknown. This technique is especially
helpful when trying to match the gain of two oppo
site polarity devices (NPN vs PNP).
I. Calibrate the oscilloscope vertical axis for 1 volt
full scale and the horizontal axis for 30 volts
full scale.
2. Adjust the oscilloscope positioning controls to
place the CRT trace (dot, with no inputs) within
the center circle of the special graticule.
3. Adjust 501 SWEEP VOLTAGE until the trace
sweeps out to either edge of the graticule, de
pending on which position the POLARITY switch
is set.
4. Set VERTICAL SENSITIVITY to the 2 mA posi
tion.
5. Set STEP SELECTOR to the 10 ,uA position.
NPN transistors will now display curves in the
upper right-hand quarter of the graticule, and PNP
in lower left-hand quarter. The polarity of an un
known device can immediately be determined by
inserting it into either socket, switching to that sock
et, and throwing the SOI POLARITY switch back and
forth until curves appear, noting its position (See
Figure 14). Once curves are displayed, the STEP
SELECTOR may need readjustment to bring all 6
into view on the screen. Note that when POLARITY
is set to PNP for an NPN device and vice versa, a
CRT trace positioned
ot center of graticule.
12
8) .......... ( ..... 1 .....
! ' . .
i
.
POLARITY switch in NPN
position (curves displayed) "'{
4) ........... ;, .. , ....... : ... , ... .
.
.
.
,��1,···1
+
ii'
!
i
LL;L:;;L
i
4/
. ... ) . ... .
j .....
)
......
(
.
,otltlon (polltlon a length
i
J : :
1
:
··r ..
1
�i
wr
1
I
-1�·········: .......... :-.......... : ........... : .. , ....... �........
. ....................... +i5
Vc(vo1tsl
Bi
: : : :
i . !.
......
J .......... L ....... ·l·
........
J,,
.
.
.
.
i
.
POLARITY switch 'in NPN
.
'
'
,.,uion (p.,.ltion a length
,
........... j .........
1,·
........... , .........
.
of cur-.e may vary)
'
'
i
4j,
.......... , .........
·
.. ........ · ..... ....
·
...........
·
...........
·
·+·
'
...
:,,,,
....... ; ........... ; ......... .. ..
le
o:
(ma)
L
..,,,,,,
�±::::::::i
=::
±::::1 .
• 15
....... ) POLARITY switch In PNP
, position (curves displayed)
.... ) .......... : ........... ; ........... : ........... !
Figure 14. Determining Transistor Polarity
I
;