Designing Hardware for QuickUSB
FX2128
Pin
QUSB2
Pin
Name
Dir
Desc
Function
108 58 PE0
/
DATA0 /
MOSI
I/O
Port E, Bit 0
Multifunction Pin
PE0 (default) is a bi-directional
general purpose I/O port. Enabled
when SETTING_FIFO_CONFIG[1:0]
='00', '10', or '11'
DATA0 is the data output signal for
serial FPGA configuration.
Automatically switches functionality
when using the FPGA configuration
commands.
MOSI is the Master-Out Slave-In data
signal for the SPI port. Automatically
switches functionality when using the
SPI commands.
109
60
PE1 / DCLK
/ SCK
I/O
Port E, Bit 1
Multifunction Pin
PE1 (default) is a bi-directional
general purpose I/O port. Enabled
when SETTING_FIFO_CONFIG[1:0]
='00', '10', or '11'
DCLK is the clock output signal for
serial FPGA configuration.
Automatically switches functionality
when using the FPGA configuration
commands.
SCLK is the clock output signal for
the SPI port. Automatically switches
functionality when using the SPI
commands.
110
62
PE2 / nCE
I/O
Port E, Bit 2
Multifunction Pin
PE2 is a bi-directional general
purpose I/O port. Enabled when
SETTING_FIFO_CONFIG[1:0] ='00',
'10', or '11'
nCE is available for use as a Chip
Enable signal for SPI commands. It is
controlled using the normal GPIO
function calls.
111 64 PE3
/
nCONFIG
I/O
Port E, Bit 3
Multifunction Pin
PE3 (default) is a bi-directional
general purpose I/O port. Enabled
when SETTING_FIFO_CONFIG[1:0]
='00', '10', or '11'
nCONFIG is the Configure/Program
output signal for serial FPGA
configuration. Automatically switches
functionality when using the FPGA
configuration commands.
112 66 PE4
/
nSTATUS
I/O
Port E, Bit 4
Multifunction Pin
PE4 (default) is a bi-directional
general purpose I/O port. Enabled
when SETTING_FIFO_CONFIG[1:0]
='00', '10', or '11'
nSTATUS is the Status input signal
for serial FPGA configuration.
Automatically switches functionality
when using the FPGA configuration
commands.
30
QuickUSB Pin Definitions