Bitwise QuickUSB, Руководство пользователя

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Designing Hardware for QuickUSB
Internally
Sourced IFCLK
Externally
Sourced IFCLK Parameter Description
Min Max Min Max
Unit
tIFCLK IFCLK Period 20.83 20.83 200 ns
tSRD SLRD to Clock Set-up
Time
18.7 12.7 ns
tRDH Clock to SLRD Hold
Time
0 3.7 ns
tOEon SLOE Turn-on to FIFO
Data Valid
10.5 10.5 ns
tOEoff SLOE Turn-off to FIFO
Data Hold
10.5 10.5 ns
tXFLG Clock to FLAGS Output
Propagation Delay
9.5 13.5 ns
tXFD Clock to FIFO Data
Output Propagation
Delay
11 15 ns
tSWR SLWR to Clock Set-up
Time
18.1 12.1 ns
tWRH Clock to SLWR Hold
Time
0 3.6 ns
tSFD FIFO Data to Clock Set-
up Time
9.2 3.2 ns
tFDH Clock to FIFO Data
Hold Time
0 4.5 ns
tSFA FIFOADR and nSLCS
to Clock Set-up Time
25 ns
tFAH Clock to FIFOADR and
nSLCS Hold Time
10 ns
tFAFLG FIFOADR to FLAGS
Output Propagation
Delay
10.7 ns
tFAFD FIFOADR to FIFO Data
Bus Propagation Delay
14.3 ns
tSPE PKTEND to Clock Set-
up Time
14.6 8.6 ns
tPEH Clock to PKTEND Hold
Time
0 2.5 ns
Table 4 – Synchronous Slave FIFO Timing Parameters
18 High Speed Parallel Port