7
TLX Matrix Switch Interfaces
thinklogical
Rev. H
–
Jan. 2019
The TLX Switch Interfaces
Documentation
This document describes the serial and network interfaces for Thinklogical's
®
TLX family of
Matrix Switches. Further documentation is available concerning the ASCII interface API, SNMP
MIB definitions and other information on the Thinklogical
®
web site. Other manuals and Quick
Start Guides may also be downloaded from our web site:
http:/www.thinklogical.com/user_manuals
Related documents:
Manual_TLX_Matrix_Switch_ASCII_API_V5
Manual_Configuring_The_TLX_ASCII_Interface
Manual_TLX_Matrix_Switch_SNMP_Traps
Matrix Switch SNMP MIB definition files that are available for downloading:
Byte Order for the
‘Switch Connection Status Broadcast’ on Port 17564
Warning!
The 16-bit values documented here store the most significant byte first.
This is called Big Endian format.
(For example, a hexadecimal value of 1235H is
stored with 12H in byte zero and 23H in byte one.)
Big Endian -
The most-significant byte of a multi-byte value is stored first, followed by lesser
significant bytes, and ending with the least-significant byte.
Example:
0x12345678
is stored as
12 34 56 78
.
Little Endian -
The least-significant byte of a multi-byte value is stored first, followed by more
significant bytes, and ending with the most-significant byte. This is the format used by x86
processor family.
Example:
0x12345678
is stored as
78 56 34 12
.
If your receiving system is not a Big Endian CPU (Intel processors are not), then
you will have to swap the byte order before you can use the value.
If you don't
swap the bytes, then a value of 1 from the switch will be interpreted as 256, 2 as 512,
and 640 as 32770.
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