BCM SL620, Руководство пользователя

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4. BIOS Setup
disabled, performance is slightly slower, but more reliable. Choices are Enabled, Disabled.
4.5.11 PCI Delay Transaction
The shipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1.
The choice: Enabled, Disabled.
4.5.12 ISA Bus Clock Frequency
You can set the speed of the AT bus at one-third or one-fourth of the CPU clock speed. The
choice: 7.159MHz, PCICLK/3, PCICLD/4
4.5.13 SDRAM CAS latency
You can select CAS latency time in HCLKs of 2/2 or 3/3. The system board designer should
set the values in this field, depending on the DRAM installed. Do not change the values in
this field unless you change specifications of the installed DRAM or the installed CPU.
4.5.14 System BIOS Cacheable
Select Enabled allows caching of the system BIOS ROM at F000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result.
4.5.14 Video RAM Cacheable
Select Enabled allows caching of the video RAM, resulting in better system performance.
However, if any program writes to this memory area, a system error may result.
4.5.15 Memory Hole at 15M-16M
In order to improve performance, certain space in memory can be reserved for ISA cards.
This memory must be mapped into the memory space below 16 MB. You can reserve this
area of system memory for ISA adapter ROM. When that area is reserved it cannot be
cached. The user information of peripherals that need to use this area of system memory
usually discusses their memory requirements.
4.5.16 AGP Aperture Size
Select the size of the Accelerated Graphics Port (AGP) aperture. The aperture is a portion of
the PCI memory address range dedicated for graphics memory address space. Host cycles
that hit the aperture range are forwarded to the AGP without any translation. See
www.agpforum.org for AGP information.