3.2.8 Decode circuit
1. Decode circuit block diagram is shown as in the following figure 3.2.8.1:
- 88 -
4. Key point voltage (unit: V) is shown as the following table:
Key point
Position
Normal working voltage (V)
Volateg change when disc out (V)
SP+
Pin 11 of D5954, pin 6of cn107
3.79
3.79
0.70
1.80
SP-
Pin 12 of D5954, pin 5 of cn107
1.38
1.38
3.40
1.80
OP+
Pin 36 of MT1389
1.38
1.38
3.10
1.80
OP-
Pin 35 of MT1389
1.53
1.53
3.08
1.98
OPO
Pin 34 of MT1389
2.44
2.44
0.40
2.50
ADIN
Pin 50 of MT1389
2.44
2.41
0.41
2.44
DMSO
Pin 5 of D5954
1.42
1.42
VIP4
Pin 30 of MT1389
1.41
1.41
SDRAM
SDCLK
SDCKE
DCS
DRAS
SWE
DQM0
DQM1
DQ0~DQ15
MA0~MA11
URST
PWR
PRD
PCE
A0~A20
AD0~AD7
MT 1389
FLASH
EEPROM
24C02
SDA
SCL
Reset
circuit
Clock
1.8V
voltage
regulating
U
1
V18
27M
Figure 3.2.8.1 Decode circuit block diagram
2. Working principle: this decode circuit is mainly composed of MT1389, SDRAM and FLASH.
Working condition of decode circuit has:
(1) Reset: refer to reset circuit working principle for details.
(2) Clock: this system adopts 27M external clock input, and produces clock signal required by
system inside through internal frequency doubling circuit.