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12. Digital Decoder R763826
12.3 Technical Description
12.3.1 General
Introduction
This decoder board is connected to the Input Selection 1 and 2 boards and accepts video (CVBS), S-video (Y/C) and component
signals. These signals are entered via the programmable 5-cable BNC inputs. It is obvious that either a computer RGB signal or a
video signal can be selected. The SAA7118E is a multi-standard video decoder chip with additional component processing providing
an optionally scaled video output. The circuit is fully I²C-bus controlled.
12.3.2 Functional Description
Analog input section
The SAA7118E has sixteen analog inputs, four analog main channels with source switching, a clamp circuit, an analog amplifier,
alias-filter and finally a 9-bit CMOS Analog to Digital Converter.
The clamp control circuit controls the clamping to the correct levels for the ADC’s. The coupling capacitor is used to store and filter
the clamping voltage.
The gain control circuit receives the static gain levels via I²C or the gain is adjusted via a built-in AGC. The AGC active time is the
sync bottom of the video signal.
Components are manually adjusted. Signal peal control limits the gain at signal overshoots.
During the vertical blanking period, gain and clamping controls are frozen to avoid influences of digital data and anti-copy encoded
signals.
The alias filter has a roll-off starting at about 6 MHz and -30dB at 12Mhz.
Chrominance path.
The 9-bit CVBS or Chrominance input is supplied to the input of a quadrature demodulator. Two time multiplexed (0° and 90° phase
relationship to the demodulator axis) are therefor generated by the SUBCARRIER GENERATION 1 block. The (time multiplexed)
output signals are then passing a low pass filter to achieve the desired bandwidth.
The filtered signals are now fed to an Adaptive Comb Filter where the chrominance signals are separated from the luminance. This
block is bypassed for Secam and during the Vertical Blanking Interval (VBI). A second low pass filter allows to shape the bandwidth
of the chrominance without affecting the luminance.
SECAM signals are processed by the SECAM PROCESSING block and it is bypassed for quadrature modulated signals.
Next is a “Chroma gain control” section amplifying or attenuating the signals according to the detected burst amplitude in the “Burst
Processing” block. This block achieves following tasks:
• burst gating
• color identification and color killing
• comparison nominal / actual burst amplitude
• loop filter chrominance gain control
• loop filter chrominance PLL
• PAL/SECAM sequence detection, generation of H/2 signal
The output of this block is used to generate a stable phase-locked sine signal under all conditions.
The PAL DELAY LINE block eliminates crosstalk between the chrominance channels. The embedded line delay is also used for
Secam recombination with the help of the fH/2 switch signal.
The CB-CR signals are now fed to the last decoder output control block, the “brightness / contrast / saturation control” block.
Luminance path.
The rejection of the chrominance components within the 9-bit CVBS is achieved by subtracting the re-modulated chrominance from
the CVBS input.
The comb filtered CR-CB are interpolated (upsampled) and then multiplied by two time multiplexed subcarrier signals. Because
the component at the adaptive comb filter output are delayed, these time multiplexed oscillator signals must also be delayed with a
time dependent on the color system and the comb filter setting. The re-modulated CR and CB signals are then added to build the
re-modulated chrominance (CHR) signal, ready for substraction.
In the last block, the separated luminance can be modified by applying a peaking or resolution enhancement . This peaking can be
fixed value or user controllable.
Matrix - Down Formatter - Multiplexing.
A matrix converts the RGB signals from the analog-to-digital converters to the Y-CB-CR format. Component input signals are by-
passed after delay compensation.
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