TROUBLESHOOTING
TESTS
5 - 8
I-E96-221A
®
TESTS
00 - Switches and LEDs
The byte values of the two switches are exclusive OR'd and the
result displayed on the LEDs. The 0 and 1 states of each pole
on both switches are summed, and the status LED is turned off
for an even sum or turned on (green) for an odd sum.
01 - CPU Test
The CPU test verifies that the processor instruction set is oper-
ational.
02 - ROM Test
The ROM test calculates a checksum value of the EPROM and
verifies that this value matches the checksum value which was
stored in the EPROM during EPROM programming.
04 - Static RAM Test
In this test, data words containing fifteen 0s and one 1 are
written and read from the full range of static RAM. The 1 is
then shifted to the next of 16 bit places and the new data word
is written and read from RAM. Similarly, a zero test is exe-
cuted. Next, all RAM is cleared and verified, then all RAM is set
and verified. The test includes byte, word and long word
accesses.
09 - Module Bus/Controlway Test
After initializing the Controlway integrated circuit, this test
sends a series of bytes to the module bus in loopback mode.
The module address and bus speed are determined by
dipswitch SW3. The timing and status of the transfer must be
within tolerance.
0A - Timer Interrupt Test
This test initializes the timer for a one-millisecond timer inter-
rupt, then waits for the timer interrupt event to occur. The test
fails if a second interrupt does not occur within 1.008 millisec-
onds.
0B - Dispatcher Interrupt Test
This test issues a software dispatcher request (sets latch) and
waits for an interrupt to occur. If an interrupt does not occur,
the test fails.
