![AXIOMTEK SBC81613 Скачать руководство пользователя страница 56](http://html1.mh-extra.com/html/axiomtek/sbc81613/sbc81613_user-manual_3037589056.webp)
SBC81613 Socket 370 All-in-One CPU Card Series User
’
s Manual
BIOS Configuration
48
7.5 Chipset
Features
Setup
This Setup menu controls the configuration of the motherboard
chipset.
Phoenix – AwardBIOS COMS Setup Utility
Advanced Chipset Features
DRAM Timing By SPD
[Enabled]
Item Help
X DRAM Clock
[Host CLK]
X DRAM Cycle Length
3
Menu Level
f
X Bank Interleave
Disable
Memory Hole
[Disabled]
P2C/C2P Concurrency
[Enabled]
Enabled adds a
Fast R-W Turn Around
[Enabled]
Parity check to the
System BIOS Cacheable
[Disabled]
boot-up memory
Video RAM Cacheable
[Disabled]
tests. Select
Frame Buffer Size
[16M]
Enabled only if the
AGP Aperture Size
[64MB]
system DRAM
AGP-4X Mode
[Enabled]
Contains parity
AGP Driving Control
[Auto]
X AGP Driving Value
DA
OnChip USB
[Enabled]
USB Keyboard Support
[Disabled]
OnChip Sound
[Auto]
CPU to PCI Write Buffer
[Enabled]
PCI Dynamic Bursting
[Enabled]
PCI Master 0 WS Write
[Enabled]
PCI Delay Transaction
[Enabled]
PCI#2 Access #1 Retry
[Disabled]
AGP Master 1 WS Write
[Diasbled]
AGP Master 1 WS Read
[Disabled]
ÇÈÆÅ
: Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
z
DRAM Clock
Set DRAM clock speed.
z
DRAM Timing By SPD
This item allows you to select the value in this field,
depending on whether the board has paged DRAMs or EDO
(extended data output) DRAMs.