AVTECH ELECTROSYSTEMS AVRQ-4-B, Инструкция по эксплуатации

Страница: 45 / 75

TYPICAL WAVEFORMS FOR STANDARD DAUGHTERBOARDS
BASIC THEORY
The user will install a DUT on a daughterboard. The daughterboard configuration
determines the input bias to the opto-coupler, as well as the output loading.
The AVRQ-4-B front panel settings control whether the positive or negative pulse
generator circuit is active internally.
The AVRQ-4-B front panel settings also control the DC voltage applied to VCC2 (+3V to
+8V, or to +43V with the -SCHB option, 150 mA maximum). This is the opto-coupler
output-side bias. GND2 is connected to chassis ground.
The opto-coupler input-side bias is controlled by the circuitry installed on the
daughterboard, as explained in previous sections. If a non-zero voltage or current bias
is required, then an A23-type 12V battery must be installed in the battery holder on the
daughterboard. (Please note that A23 batteries have a limited mA·hr rating – typically
30 mA·hr when operating at 15 mA – so the battery should be removed immediately
after testing, and its output should verified to be between 6V and 12V before each test.)
As an example, the HV pulse might be set to a positive amplitude (+1.5 kV), with the
input anode and cathode both connected to GND1 (zero current bias). In this mode, the
output voltage should be pulled-up to VCC2. However, as the rise time of the HV pulse
is reduced, the interference caused by the fast pulse may cause a “glitch” to appear on
the output, where the output changes state (or come close to it). This is illustrated
below:
The next illustration shows a similar glitch occurring for a negative high-voltage pulse,
where the input has been biased “on” to provide a normally-zero output voltage:
45
HV PULSE
AMP1,
+1.5 kV
RISE TIME,
VARIABLE
LOGIC OUT
V
CC
(AMP2),
+3V TO +43V
GLITCH CAUSED BY
INADEQUATE COMMON
MODE TRANSIENT
IMMUNITY (CMTI)