AVTECH ELECTROSYSTEMS AVRQ-4-B, Инструкция по эксплуатации

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R9 - Zero-Ohm Jumper to connect DUT pin 2 to GND1
R10 - Zero-Ohm Jumper to connect DUT pin 3 to GND1
R11 - Zero-Ohm Jumper to connect DUT pin 4 to GND1
P1
PAD-SM - Unused pads.
P2
BT1 KEYSTONE2470 -
One user-installed A23-type 12V battery, prime power for
VCC1.(Please note that A23 batteries have a limited mA·hr
rating – typically 30 mA·hr when operating at 15 mA – so the
battery should be removed immediately after testing, and its
output should verified to be between 6V and 12V before each
test.)
J6 P6246-PROBE A34264-02-ND No
Optional logic probe point circuit
C9
0805
-
Optional R12 -
R13 -
SO-8 DAUGHTERBOARD (PCB 314A)
Units with the -SO8 option are provided with 32 additional unpopulated (bare)
daughterboards (PCB 314A), suitable for use with standard SO-8 packages. These
PCBs require assembly.
These PCBs are essentially identical to PCB 267D described in the previous section,
except that the 8-pin DIP socket is replaced with a footprint for an SO-8 package. The
user will need to solder the devices directly to the PCB, limiting the number of times
that each PCB and device can be used. CAM files are available, so that the user may
produce additional daughterboards as required:
https://www.avtechpulse.com/semiconductor/avrq-4/#support_files
CUSTOM DAUGHTERBOARDS
The daughterboards provided with the AVRQ-4-B are meant as samples.
The user may construct their own daughterboards, which may incorporated a preferred
physical layout, different bias circuits, or different DUT packages and socketing.
When designing your own daughterboard, take care to isolate the input and output
sides as much as possible, to both provide sufficient high-voltage clearance and to
minimize parasitic coupling of the HV pulse onto the output signal.
If the user designs a custom daughterboard, the same connections must be made to
the pins of the daughterboard. That is, pins 3, 7, 12, and 16 on J1 (GND1) must be
shorted together, VCC2 must go to J1:1, GND2 to J1:13-16 (and J3, J4, J5), and the logic
output to J1:8.
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