Avnet Zynq Mini-ITX, Руководство пользователя

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2
3 Reference Design Block Diagram
The following figure shows a high-level block diagram of the reference design. The
reference design is intended to show how to connect the ARM DSTREAM debug adapter
to the Zynq Mini-ITX board via the ARM PJTAG port.
The ARM PJTAG port is NOT connected to the Zynq dedicated PJTAG pins on the Zynq
Mini-ITX board, it is connected to the Zynq PL pins (referred to as EMIO pins). So, prior
to connecting the ARM DSTREAM debug adapter to the Zynq Mini-ITX board, a design
that connects the ARM PJTAG port to the ARM processor via the PL pins must be must
be loaded in to the Zynq device. This reference design implements the connection of the
ARM PJTAG port to the ARM processor via the PL pins. Users can use the steps taken in
this design to include the ARM PJTAG interface in their own design running on the
Avnet Zynq Mini-ITX board.
Figure 1 – Reference Design Block Diagram