16
Avago Technologies Confi dential. Restricted under NDA
Schematic: Revision 3.0 Board (Cont.)
S1
RESET
GND
GND
SCL
SDA
1
J14
SCL
1
J15
SDA
Vcc33
R3
5k
R2
5k
RESET
GND
1
SDA
2
+5V
3
SCL
4
JTWS
I2C_CON
1
J16
GND
GND
Value change
1
1
2
2
R6 5k
Vcc33
GND
Vcc33
1
2
3
4
5
6
J24
JTAG
MISO
SCK
Ureset
MOSI
INTL
1
J17
INTL
R1
5k
Vcc33
TO
S
C
2
AM
U
X
0
AM
U
X
1
R15
OPRN
Vcc33
R16
OPEN
GND
R17
OPEN
Vcc33
R19
OPEN
Vcc33
R20
OPEN
GND
1
J28
A
m
u
x
0
1
J29
A
m
u
x
1
1
J30
TOSC2
UR
E
S
E
T
R21
OPEN
Vcc33
R22
OPEN
GND
1
J31
Ureset
1
2
3
4
5
6
JP18
HEADER 2X3
GND
ADR2
ADR1
ADR0
TP2
Vcc33 Sense
TP1
Vcc25 Sense
1
J25
GND
1
J26
GND
1
J27
GND
GND
1
2
3
4
JP1
4 HEADER
2.5V
Vcc25
Vcc33
3.3V
Vcc33
Vcc25
Sense lines to be routed
fro
m
Meg-Arra
y
connector