AC4830xC-C Data Book
Chapter 3. Chip Data and Timing
Revision 1.0
45
March 2000
3.3.4 Host Port Interface Timing
3.3.4.1 Host Port Interface Switching Characteristics
Table
3-14: Host Port Interface Switching Characteristics
Parameter (units ns)
Min
Max
(81) Delay time, HCDS- low to HD valid
2
16
(82) Delay time, HRWR- falling to HD valid for first byte of a non-
subsequent read: max. 20 ns
During Kernel Download Mode (CLKOUT = 10 MHz):
case 1: if (95) <350 ns
case 2: if (95) >350 ns
360
20**
During Other Modes (CLKOUT = 100 MHz):
case 1: if (95) <35 ns
case 2: if (95) >35 ns
45
20**
(83) Delay time, HCDS- low to HD valid, second byte
5
20
(84) Delay time, HCDS- high to HRDY high (CLKOUT = 100 MHz)
60**
(85) Setup time, HD valid before HRDY rising edge (CLKOUT =100 MHz)
5**
(86) Hold time, HD valid after HCDS- rising edge
0
12*
(87) Delay time, CLKOUT rising edge to HRDY high
10**
(88) Delay time, HRWR- or HCS- high to HRDY low
12**
(89) Delay time, CLKOUT rising edge to HIN change
15
* Values are derived from characterization data and not tested.
** Values are ensured by design but not tested.
Notes:
For Table 3-14
1. HRS stands for HRS0, HRS1 and HR/W-; HRWR- refers to either HRD- or HWR-; HCDS- refers to
the logical OR of HCS- and HRWR-.
2. On Host read accesses to the HPI, the setup time of HD before the HCDS- rising edge depends on
the Host waveforms and cannot be specified here.
3. HRDY is not valid when the RESET is asserted (during kernel download).
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