AC4830xC-C Data Book
Chapter 2. Functional Description
Revision 1.0
23
March 2000
2.2.6 Test Access Port
The Test Access Port (TAP) is the boundary scan interface that is fully compliant with
the standard IEEE 1149.1.
Five pins are available for this interface:
TCK
- Test Clock. Free running clock with 50% duty cycle.
TDI
- Test Data Input. TDI is clocked into the selected internal port register on rising
edge of TCK.
TDO
- Test Data Output. The contents of the selected internal port register is shifted
out of TDO on falling edge of TCK. TDO is in high impedance state, except
when the scanning of data is in progress.
TMS
- Test Mode Select. Serial control input is clocked into the Test Access Port
internal controller on rising edge of TCK.
TRST-
- Test Reset. When high, gives the IEEE 1149.1 scan system control of the
operation of the AC4830xC-C. When low or not connected (pin is internally
pulled-down), the device operates in its functional mode, and the IEEE
standard 1149.1 signals are ignored.
See Figure 2-8 below for the TAP interface.
Figure
2-9: AC4830xC-C Test Access Port Interface
HPI
TDO
AC4830xC-C
TCK
VOICE
Interface
MEMORY
& I/O
I/F
Test
Access
Port
TDI
TMS
TRST-
Содержание AC4830 C-C Series
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