AC4830xC-C Data Book
Chapter 2. Functional Description
Revision 1.0
19
March 2000
2.2.4 Memory, I/O and CAS Interface
The AC4830xC-C requires one 64K x 16 SRAM device. For an example and
description of such a memory device, see Chapter 4, “Application Notes”.
The same Memory interface supports general purpose I/O ports. The I/O ports are
driven by 4-bit port In/Out buffers controlled by the SIGEN-. After the User issues the
Run command, the SIGEN- pin is asserted to “Low” level. The SRAM provides run-
time data storage. Figure
2-6 below, illustrates the signals of the Memory Interface.
Figure
2-6: AC4830xC-C Memory & I/O Interface Signals
HPI
AC4830xC-C
R/W-
MS-
A0-A15
D0-D15
IOS-
SIGEN-
MEMORY
& I/O
Interface
VOICE
Interface
TAP
A
A
1
2
2
1
B
B
CAS
(E&M)
Port
The AC4830xC-C handles E&M signals through an external I/O CAS (E&M) port, by
means of I/O strobe (IOS-), read/write (R/W-) and data bus lines, as shown above in
Figure
2-6.
It samples the E&M input (E) signals with a 1 ms resolution and transmits their values
to the remote side (receiving side) through the Host Port Interface (HPI) shown in
Section 2.2.3.
The AC4830xC-C receives from the remote side, the E&M output (M) signals, and
sends them to the I/O interface.
The output port is controlled by the SIGEN- pin, which keeps the I/O port in tri-state
until the processor enters the Active state. Signaling information is exchanged through
the data pins, and controlled by means of pins IOS- and R/W-.
MS- is the Memory strobe, and is used to indicate an external bus access to data or
program memory.
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