AT90S/LS4434 and AT90S/LS8535
49
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Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable signal (EEWE) is the write strobe to the EEPROM. When address and data are correctly set
up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical “1” is
written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the
EEPROM (the order of steps 2 and 3 is unessential):
1.
Wait until EEWE becomes zero.
2.
Write new EEPROM address to EEARL and EEARH (optional).
3.
Write new EEPROM data to EEDR (optional).
4.
Write a logical “1” to the EEMWE bit in EECR (to be able to write a logical “1” to the EEMWE bit, the EEWE bit must
be written to “0” in the same cycle).
5.
Within four clock cycles after setting EEMWE, write a logical “1” to EEWE.
Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will
time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR and EEDR reg-
isters will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag
cleared during the four last steps to avoid these problems.
When the write access time (typically 2.5 ms at V
CC
= 5V or 4 ms at V
CC
= 2.7V) has elapsed, the EEWE bit is cleared
(zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has
been set, the CPU is halted for two clock cycles before the next instruction is executed.
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Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable signal (EERE) is the read strobe to the EEPROM. When the correct address is set up in the
EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the
EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE
has been set, the CPU is halted for four clock cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or
address is written to the EEPROM I/O registers, the write operation will be interrupted and the result is undefined.
Prevent EEPROM Corruption
During periods of low V
CC
,
the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the
EEPROM to operate properly. These issues are the same as for board level systems using the EEPROM and the same
design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence
to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incor-
rectly, if the supply voltage for executing instructions is too low.
EEPROM data corruption can easily be avoided by following these design recommendations (one is sufficient):
1.
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This is best done by an exter-
nal low V
CC
Reset Protection circuit, often referred to as a Brown-out Detector (BOD). Please refer to application
note AVR 180 for design considerations regarding power-on reset and low-voltage detection.
2.
Keep the AVR core in Power-down Sleep Mode during periods of low V
CC
. This will prevent the CPU from attempting
to decode and execute instructions, effectively protecting the EEPROM registers from unintentional writes.
3.
Store constants in Flash memory if the ability to change memory contents from software is not required. Flash
memory cannot be updated by the CPU and will not be subject to corruption.
