AT90S/LS4434 and AT90S/LS8535
44
Asynchronous Status Register – ASSR
•
Bit 7..4 – Res: Reserved Bits
These bits are reserved bits in the AT90S4434/8535 and always read as zero.
•
Bit 3 – AS2: Asynchronous Timer/Counter2
When AS2 is set (one), Timer/Counter2 is clocked from the TOSC1 pin. Pins PC6 and PC7 become connected to a crystal
oscillator and cannot be used as general I/O pins. When cleared (zero), Timer/Counter2 is clocked from the internal system
clock, CK. When the value of this bit is changed, the contents of TCNT2, OCR2 and TCCR2 might get corrupted.
•
Bit 2 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set (one). When TCNT2 has been
updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in this bit indicates that
TCNT2 is ready to be updated with a new value.
•
Bit 1 – OCR2UB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set (one). When OCR2 has been
updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in this bit indicates that
OCR2 is ready to be updated with a new value.
•
Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set (one). When TCCR2 has been
updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in this bit indicates that
TCCR2 is ready to be updated with a new value.
If a write is performed to any of the three Timer/Counter2 registers while its Update Busy flag is set (one), the updated
value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2 and TCCR2 are different. When reading TCNT2, the actual timer value is
read. When reading OCR2 or TCCR2, the value in the temporary storage register is read.
Asynchronous Operation of Timer/Counter2
When Timer/Counter2 operates asynchronously, some considerations must be taken.
• Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers
TCNT2, OCR2 and TCCR2 might get corrupted. A safe procedure for switching clock source is:
1.
Disable the Timer/Counter2 interrupts OCIE2 and TOIE2.
2.
Select clock source by setting AS2 as appropriate.
3.
Write new values to TCNT2, OCR2 and TCCR2.
4.
To switch to asynchronous operation: Wait for TCN2UB, OCR2UB and TCR2UB.
5.
Clear the TOV2 and OCF2 flags in TIFR.
6.
Enable interrupts, if needed.
• The oscillator is optimized for use with a 32,768 Hz watch crystal. An external clock signal applied to this pin goes
through the same amplifier having a bandwidth of 256 kHz. The external clock signal should therefore be in the interval
0 Hz - 256 kHz. The frequency of the clock signal applied to the TOSC1 pin must be lower than one fourth of the CPU
main clock frequency.
• When writing to one of the registers TCNT2, OCR2 or TCCR2, the value is transferred to a temporary register and
latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary
register have been transferred to their destination. Each of the three mentioned registers have their individual temporary
register. For example, writing to TCNT2 does not disturb an OCR2 write in progress. To detect that a transfer to the
destination register has taken place, an Asynchronous Status Register (ASSR) has been implemented.
Bit
7
6
5
4
3
2
1
0
$22 ($22)
–
–
–
–
AS2
TCN2UB
OCR2UB
TCR2UB
ASSR
Read/Write
R
R
R
R
R/W
R
R
R
Initial value
0
0
0
0
0
0
0
0
