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6255B–ATARM–26-Jun-09

Application Note

6.3

SMC Timings

The K9F2G08U0M is a 256 MB device connected with an 8-bit data bus width.

An accurate one-to-one comparison is necessary between NandFlash and SMC waveforms for
a complete SMC configuration.

Figure 6-1

and

Figure 6-2

show two cases that highlight all the

required timings.

Figure 6-1.

COMMAND LATCH and ADDRESS LATCH Cycle

Figure 6-2.

SERIAL ACCESS Cycle after READ

These timings are summarized in

Table 6-4

ALE/CLE

NCS

NWE_SETUP

NWE_PULSE

NWE_HOLD

NWE

NCS_WR_SETUP

NCS_WR_PULSE

NCS_WR_HOLD

NWE_CYCLE

D[31:0]

NCS

NRD_SETUP

NRD_PULSE

NRD_HOLD

NRD

D[31:0]

NCS_RD_SETUP

NCS_RD_PULSE

NCS_RD_HOLD

NRD_CYCLE

Содержание AT91SAM9

Страница 1: ...ip file Basic NAND Source Code zip the source code is based on the product libV3 2 NAND Flash Overview 2 1 General Overview NAND Flash provides a cost effective alternative to hard drives especially for portable and handheld systems The performance pricing and memory size options make it optimal for storage applications pictures audio files etc The NAND Flash used to illustrate this interface is t...

Страница 2: ...e enable OE output enable D 15 0 data bus A 20 0 address bus WP write protect NAND Flash I O device type interface composed of up to 24 pins CE chip enable WE write enable RE read enable CLE command latch enable ALE address latch enable I O 7 0 or I O 15 0 data bus WP write protect R B ready busy RE Read enable 2 2 2 Array Architecture NOR Flash is divided into blocks which typically contain many ...

Страница 3: ...k erase times are an impressive 2 ms for NAND versus 200 ms for NOR 2 2 4 Conclusion Table 2 2 summarizes NAND NOR advantages and disadvantages Clearly NAND Flash has several significant positive attributes The one negative attribute is that it is not well suited for direct random access Table 2 1 Differences in Performance Characteristics NAND Flash K9F2G08U0M NOR Flash AT49BV16x4 90 Random acces...

Страница 4: ...ystem software must create a map of invalid memory blocks If the application code executes from RAM rather than Flash memory system software bad block mapping is only necessary at boot time and during Flash storage updates All device locations are erased FFh for X8 FFFFh for X16 except locations where the invalid block information is written prior to shipping The invalid block status is defined by...

Страница 5: ...nd ALE control Flash device READ and WRITE operations CE is used to enable the device When CE is low and the device is not in the busy state the Flash memory accepts command data and address information When the device is not performing an operation the CE pin is typically driven HIGH and the device enters standby mode The memory enters standby if CE goes HIGH while data is being transferred and t...

Страница 6: ... I O 7 0 for x8 devices and I O 15 0 on x16 devices 4 6 Ready Busy The R B output provides a hardware method of indicating the completion of a PRO GRAM ERASE READ operation The signal is typically high and transitions to low after the appropriate command is written to the device A dedicated PIO should be assigned to this signal with a pull up resistor for proper operation Alternatively the READ ST...

Страница 7: ... types exists those who are CE don t care and those who are not For CE don t care NAND the chip enable state is don t care during the busy period preceding the data read cycle Thus allowing this flash to be connected to active memory buses such as the AT91 memory bus For standard NAND the CE signal remains asserted even when NCS3 is not selected prevent ing the device from returning to standby mod...

Страница 8: ...gh A21 ALE Address Latch Enable Output High PIOx CE Chip Enable 1 2 Output Low PIOy RDY BSY Ready Busy 1 Input Low Table 5 3 ALE CLE Management ALE CLE AT91SAM9261 Memory Address Offset AT91SAM9260 Memory Address Offset NAND Register Selected 0 0 0x000000 0x000000 DATA register 0 1 0x200000 0x400000 COMMAND register 1 0 0x400000 0x200000 ADDRESS register 1 1 0x600000 0x600000 Undefined Don t use D...

Страница 9: ...Table 6 1 System Configuration Description Settings Register field Value System PLL frequency 198 MHz PMC_PLLAR 0x20603F09 Processor Bus Clock 198 99 MHz PMC_MCKR 0x00000102 EBI Chip Select Assignment NAND EBI_CSA EBI_CS3A 0x8 Table 6 2 Peripheral Configuration for Standard NAND on AT91SAM9261 Description Settings AT91 libV3 Function NANDOE and NANDWE are respectively PC0 and PC1 Output AT91F_PIO_...

Страница 10: ...ete SMC configuration Figure 6 1 and Figure 6 2 show two cases that highlight all the required timings Figure 6 1 COMMAND LATCH and ADDRESS LATCH Cycle Figure 6 2 SERIAL ACCESS Cycle after READ These timings are summarized in Table 6 4 ALE CLE NCS NWE_SETUP NWE_PULSE NWE_HOLD NWE NCS_WR_SETUP NCS_WR_PULSE NCS_WR_HOLD NWE_CYCLE D 31 0 NCS NRD_SETUP NRD_PULSE NRD_HOLD NRD D 31 0 NCS_RD_SETUP NCS_RD_...

Страница 11: ...NWE Pulse N A CE is a PIO line 3 tCS 35 NWE Setup NWE Pulse N A CE is a PIO line 4 tDS 20 NWE Setup NWE Pulse NWE Setup NWE Pulse 2 tCEA 45 Not programmable Not programmable tREA 30 Not programmable Not programmable tRR 20 managed by software managed by software Hold tCLH 10 NWE Hold NWE Hold 1 tALH 10 NWE Hold NWE Hold 1 tCH 10 NWE Hold N A CE is a PIO line 1 tDH 10 Data Float Time Data Float Tim...

Страница 12: ...ble 6 5 gives SMC register configurations other fields keep the reset values Table 6 5 SMC NCS3 Configuration Description Settings Register field Value NWE and NRD Setup 1 cycle SMC_SETUP 3 0x01010101 NRD and NWE Pulse length 3 cycles SMC_PULSE 3 0x03030303 NRD and NWE Cycle length 5 cycles SMC_CYCLE 3 0x05050505 Chip Select Control SMC_CTRL 3 0x00020003 Read Mode NRD READ_MODE 0x1 Write Mode NWE ...

Страница 13: ...s an input and enable the clock of this PIO to manage the Ready Busy signal Configure Static Memory Controller CS3 Setup Pulse Cycle and Mode depending on NAND Flash timings the data bus width and the system bus frequency D6 D0 D3 D4 D2 D1 D5 D7 NANDOE NANDWE ANY PIO ANY PIO ALE CLE D 0 7 3V3 3V3 2 Gb TSOP48 PACKAGE U1 K9F2G08U0M U1 K9F2G08U0M WE 18 N C 6 VCC 37 CE 9 RE 8 N C 20 WP 19 N C 5 N C 1 ...

Страница 14: ...8 1 1 NAND Flash Initialization The following actions compose the initialization phase of the CE don t Care NAND NAND Flash logic is enabled on NCS3 through EBI_CSA NAND Flash timings are programmed with SMC_SETUP3 PULSE3 CYCLE3 and MODE3 SMC registers PC13 PIO line is dedicated to handle NAND R B D6 D0 D3 D4 D2 D1 D5 D7 D14 D8 D11 D12 D10 D9 D13 D15 NANDOE NANDWE ANY PIO ALE CLE D 0 15 ANY PIO 3V...

Страница 15: ...package that performs this configuration is provided with this Application Note 8 1 2 NAND Flash Boot First it looks for a boot bin file in the root directory or in the FIRMWARE directory of a FAT12 16 formatted NAND Flash If such a file is found code is downloaded into the internal SRAM This is followed by a remap and a jump to the first address of the SRAM If the NAND Flash is not formatted the ...

Страница 16: ...e next block The SAM BA application marks a NAND Flash block as invalid by setting the BadBlock Info byte in the 8 byte Invalid Block Information structure to a value different from 0xFF This is per formed for the first two pages of each bad block The same principle has to be implemented in a user application in order to read data from a NAND Flash memory written by the SAM BA application 8 1 4 2 ...

Страница 17: ...pplication Note Revision History Doc Rev Date Comments Change Request Ref 6255A 09 Oct 06 First issue 6255B 16 Jun 09 page 1 AT91SAM AT91SAM9 Table 6 5 on page 12 NAND Flash support App Note SMC Timings are not correct 3906 5582 ...

Страница 18: ...RANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILI...

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